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target/riscv: Restore the predicate() NULL check behavior

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When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.

This actually reverts commit 0ee342256a.
Some comments are also added to indicate that predicate() must be
provided for an implemented CSR.

Reported-by: Fei Wu <fei2.wu@intel.com>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-Id: <20230417043054.3125614-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2023-04-17 12:30:54 +08:00 • committed by Alistair Francis
parent 9e1a30d342
commit eae04c4c13
1 changed files with 9 additions and 2 deletions
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11
target/riscv/csr.c
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@ -3826,6 +3826,11 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
} }
/* ensure CSR is implemented by checking predicate */
if (!csr_ops[csrno].predicate) {
return RISCV_EXCP_ILLEGAL_INST;
}
/* privileged spec version check */ /* privileged spec version check */
if (env->priv_ver < csr_min_priv) { if (env->priv_ver < csr_min_priv) {
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
@ -3843,7 +3848,6 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
* illegal instruction exception should be triggered instead of virtual * illegal instruction exception should be triggered instead of virtual
* instruction exception. Hence this comes after the read / write check. * instruction exception. Hence this comes after the read / write check.
*/ */
g_assert(csr_ops[csrno].predicate != NULL);
RISCVException ret = csr_ops[csrno].predicate(env, csrno); RISCVException ret = csr_ops[csrno].predicate(env, csrno);
if (ret != RISCV_EXCP_NONE) { if (ret != RISCV_EXCP_NONE) {
return ret; return ret;
@ -4032,7 +4036,10 @@ static RISCVException write_jvt(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
/* Control and Status Register function table */ /*
* Control and Status Register function table
* riscv_csr_operations::predicate() must be provided for an implemented CSR
*/
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */ /* User Floating-Point CSRs */
[CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags }, [CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },