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hw/misc: Introduce a model of Xilinx Versal's CFRAME_BCAST_REG

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Introduce a model of Xilinx Versal's Configuration Frame broadcast
controller (CFRAME_BCAST_REG).

Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20230831165701.2016397-7-francisco.iglesias@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Francisco Iglesias 2023-08-31 17:56:59 +01:00 • committed by Peter Maydell
parent c6766f5b75
commit eadd3343c4
2 changed files with 178 additions and 0 deletions
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17
include/hw/misc/xlnx-versal-cframe-reg.h
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@ -26,6 +26,10 @@
#define TYPE_XLNX_VERSAL_CFRAME_REG "xlnx,cframe-reg"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameReg, XLNX_VERSAL_CFRAME_REG)
#define TYPE_XLNX_VERSAL_CFRAME_BCAST_REG "xlnx.cframe-bcast-reg"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCFrameBcastReg,
XLNX_VERSAL_CFRAME_BCAST_REG)
/*
* The registers in this module are 128 bits wide but it is ok to write
* and read them through 4 sequential 32 bit accesses (address[3:2] = 0,
@ -283,4 +287,17 @@ struct XlnxVersalCFrameReg {
bool row_configured;
};
struct XlnxVersalCFrameBcastReg {
SysBusDevice parent_obj;
MemoryRegion iomem_reg;
MemoryRegion iomem_fdri;
/* 128-bit wfifo. */
uint32_t wfifo[WFIFO_SZ];
struct {
XlnxCfiIf *cframe[15];
} cfg;
};
#endif