mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 08:13:54 -06:00
Partial support for 34K multithreading, not functional yet.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3156 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
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parent
606b41e702
commit
ead9360e2f
18 changed files with 2305 additions and 826 deletions
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@ -17,21 +17,7 @@ typedef unsigned char uint_fast8_t;
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typedef unsigned int uint_fast16_t;
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#endif
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typedef union fpr_t fpr_t;
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union fpr_t {
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float64 fd; /* ieee double precision */
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float32 fs[2];/* ieee single precision */
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uint64_t d; /* binary double fixed-point */
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uint32_t w[2]; /* binary single fixed-point */
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};
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/* define FP_ENDIAN_IDX to access the same location
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* in the fpr_t union regardless of the host endianess
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*/
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#if defined(WORDS_BIGENDIAN)
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# define FP_ENDIAN_IDX 1
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#else
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# define FP_ENDIAN_IDX 0
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#endif
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struct CPUMIPSState;
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typedef struct r4k_tlb_t r4k_tlb_t;
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struct r4k_tlb_t {
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@ -48,20 +34,40 @@ struct r4k_tlb_t {
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target_ulong PFN[2];
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};
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typedef struct mips_def_t mips_def_t;
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typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
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struct CPUMIPSTLBContext {
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uint32_t nb_tlb;
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uint32_t tlb_in_use;
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int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
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void (*do_tlbwi) (void);
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void (*do_tlbwr) (void);
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void (*do_tlbp) (void);
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void (*do_tlbr) (void);
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union {
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struct {
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r4k_tlb_t tlb[MIPS_TLB_MAX];
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} r4k;
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} mmu;
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};
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typedef struct CPUMIPSState CPUMIPSState;
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struct CPUMIPSState {
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/* General integer registers */
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target_ulong gpr[32];
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/* Special registers */
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target_ulong PC;
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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target_ulong t0;
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target_ulong t1;
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target_ulong t2;
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typedef union fpr_t fpr_t;
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union fpr_t {
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float64 fd; /* ieee double precision */
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float32 fs[2];/* ieee single precision */
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uint64_t d; /* binary double fixed-point */
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uint32_t w[2]; /* binary single fixed-point */
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};
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/* define FP_ENDIAN_IDX to access the same location
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* in the fpr_t union regardless of the host endianess
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*/
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#if defined(WORDS_BIGENDIAN)
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# define FP_ENDIAN_IDX 1
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#else
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# define FP_ENDIAN_IDX 0
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#endif
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target_ulong HI, LO;
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typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
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struct CPUMIPSFPUContext {
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/* Floating point registers */
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fpr_t fpr[32];
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#ifndef USE_HOST_FLOAT_REGS
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@ -99,30 +105,161 @@ struct CPUMIPSState {
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#define FP_DIV0 8
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#define FP_INVALID 16
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#define FP_UNIMPLEMENTED 32
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};
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typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
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struct CPUMIPSMVPContext {
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int32_t CP0_MVPControl;
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#define CP0MVPCo_CPA 3
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#define CP0MVPCo_STLB 2
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#define CP0MVPCo_VPC 1
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#define CP0MVPCo_EVP 0
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int32_t CP0_MVPConf0;
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#define CP0MVPC0_M 31
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#define CP0MVPC0_TLBS 29
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#define CP0MVPC0_GS 28
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#define CP0MVPC0_PCP 27
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#define CP0MVPC0_PTLBE 16
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#define CP0MVPC0_TCA 15
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#define CP0MVPC0_PVPE 10
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#define CP0MVPC0_PTC 0
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int32_t CP0_MVPConf1;
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#define CP0MVPC1_CIM 31
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#define CP0MVPC1_CIF 30
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#define CP0MVPC1_PCX 20
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#define CP0MVPC1_PCP2 10
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#define CP0MVPC1_PCP1 0
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};
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typedef struct mips_def_t mips_def_t;
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#define MIPS_SHADOW_SET_MAX 16
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#define MIPS_TC_MAX 5
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#define MIPS_DSP_ACC 4
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typedef struct CPUMIPSState CPUMIPSState;
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struct CPUMIPSState {
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/* General integer registers */
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target_ulong gpr[32][MIPS_SHADOW_SET_MAX];
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/* Special registers */
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target_ulong PC[MIPS_TC_MAX];
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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target_ulong t0;
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target_ulong t1;
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target_ulong t2;
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#endif
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target_ulong HI[MIPS_DSP_ACC][MIPS_TC_MAX];
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target_ulong LO[MIPS_DSP_ACC][MIPS_TC_MAX];
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target_ulong ACX[MIPS_DSP_ACC][MIPS_TC_MAX];
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target_ulong DSPControl[MIPS_TC_MAX];
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CPUMIPSMVPContext *mvp;
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CPUMIPSTLBContext *tlb;
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CPUMIPSFPUContext *fpu;
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uint32_t current_tc;
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uint32_t nb_tlb;
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uint32_t tlb_in_use;
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uint32_t SEGBITS;
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target_ulong SEGMask;
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int (*map_address) (CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
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void (*do_tlbwi) (void);
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void (*do_tlbwr) (void);
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void (*do_tlbp) (void);
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void (*do_tlbr) (void);
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union {
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struct {
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r4k_tlb_t tlb[MIPS_TLB_MAX];
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} r4k;
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} mmu;
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int32_t CP0_Index;
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/* CP0_MVP* are per MVP registers. */
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int32_t CP0_Random;
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int32_t CP0_VPEControl;
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#define CP0VPECo_YSI 21
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#define CP0VPECo_GSI 20
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#define CP0VPECo_EXCPT 16
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#define CP0VPECo_TE 15
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#define CP0VPECo_TargTC 0
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int32_t CP0_VPEConf0;
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#define CP0VPEC0_M 31
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#define CP0VPEC0_XTC 21
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#define CP0VPEC0_TCS 19
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#define CP0VPEC0_SCS 18
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#define CP0VPEC0_DSC 17
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#define CP0VPEC0_ICS 16
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#define CP0VPEC0_MVP 1
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#define CP0VPEC0_VPA 0
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int32_t CP0_VPEConf1;
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#define CP0VPEC1_NCX 20
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#define CP0VPEC1_NCP2 10
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#define CP0VPEC1_NCP1 0
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target_ulong CP0_YQMask;
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target_ulong CP0_VPESchedule;
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target_ulong CP0_VPEScheFBack;
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int32_t CP0_VPEOpt;
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#define CP0VPEOpt_IWX7 15
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#define CP0VPEOpt_IWX6 14
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#define CP0VPEOpt_IWX5 13
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#define CP0VPEOpt_IWX4 12
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#define CP0VPEOpt_IWX3 11
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#define CP0VPEOpt_IWX2 10
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#define CP0VPEOpt_IWX1 9
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#define CP0VPEOpt_IWX0 8
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#define CP0VPEOpt_DWX7 7
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#define CP0VPEOpt_DWX6 6
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#define CP0VPEOpt_DWX5 5
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#define CP0VPEOpt_DWX4 4
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#define CP0VPEOpt_DWX3 3
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#define CP0VPEOpt_DWX2 2
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#define CP0VPEOpt_DWX1 1
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#define CP0VPEOpt_DWX0 0
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target_ulong CP0_EntryLo0;
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int32_t CP0_TCStatus[MIPS_TC_MAX];
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#define CP0TCSt_TCU3 31
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#define CP0TCSt_TCU2 30
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#define CP0TCSt_TCU1 29
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#define CP0TCSt_TCU0 28
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#define CP0TCSt_TMX 27
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#define CP0TCSt_RNST 23
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#define CP0TCSt_TDS 21
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#define CP0TCSt_DT 20
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#define CP0TCSt_DA 15
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#define CP0TCSt_A 13
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#define CP0TCSt_TKSU 11
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#define CP0TCSt_IXMT 10
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#define CP0TCSt_TASID 0
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int32_t CP0_TCBind[MIPS_TC_MAX];
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#define CP0TCBd_CurTC 21
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#define CP0TCBd_TBE 17
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#define CP0TCBd_CurVPE 0
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target_ulong CP0_TCHalt[MIPS_TC_MAX];
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target_ulong CP0_TCContext[MIPS_TC_MAX];
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target_ulong CP0_TCSchedule[MIPS_TC_MAX];
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target_ulong CP0_TCScheFBack[MIPS_TC_MAX];
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target_ulong CP0_EntryLo1;
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target_ulong CP0_Context;
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int32_t CP0_PageMask;
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int32_t CP0_PageGrain;
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int32_t CP0_Wired;
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int32_t CP0_SRSConf0_rw_bitmask;
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int32_t CP0_SRSConf0;
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#define CP0SRSC0_M 31
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#define CP0SRSC0_SRS3 20
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#define CP0SRSC0_SRS2 10
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#define CP0SRSC0_SRS1 0
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int32_t CP0_SRSConf1_rw_bitmask;
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int32_t CP0_SRSConf1;
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#define CP0SRSC1_M 31
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#define CP0SRSC1_SRS6 20
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#define CP0SRSC1_SRS5 10
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#define CP0SRSC1_SRS4 0
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int32_t CP0_SRSConf2_rw_bitmask;
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int32_t CP0_SRSConf2;
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#define CP0SRSC2_M 31
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#define CP0SRSC2_SRS9 20
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#define CP0SRSC2_SRS8 10
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#define CP0SRSC2_SRS7 0
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int32_t CP0_SRSConf3_rw_bitmask;
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int32_t CP0_SRSConf3;
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#define CP0SRSC3_M 31
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#define CP0SRSC3_SRS12 20
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#define CP0SRSC3_SRS11 10
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#define CP0SRSC3_SRS10 0
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int32_t CP0_SRSConf4_rw_bitmask;
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int32_t CP0_SRSConf4;
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#define CP0SRSC4_SRS15 20
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#define CP0SRSC4_SRS14 10
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#define CP0SRSC4_SRS13 0
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int32_t CP0_HWREna;
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target_ulong CP0_BadVAddr;
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int32_t CP0_Count;
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@ -152,8 +289,24 @@ struct CPUMIPSState {
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#define CP0St_EXL 1
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#define CP0St_IE 0
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int32_t CP0_IntCtl;
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#define CP0IntCtl_IPTI 29
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#define CP0IntCtl_IPPC1 26
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#define CP0IntCtl_VS 5
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int32_t CP0_SRSCtl;
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#define CP0SRSCtl_HSS 26
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#define CP0SRSCtl_EICSS 18
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#define CP0SRSCtl_ESS 12
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#define CP0SRSCtl_PSS 6
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#define CP0SRSCtl_CSS 0
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int32_t CP0_SRSMap;
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#define CP0SRSMap_SSV7 28
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#define CP0SRSMap_SSV6 24
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#define CP0SRSMap_SSV5 20
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#define CP0SRSMap_SSV4 16
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#define CP0SRSMap_SSV3 12
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#define CP0SRSMap_SSV2 8
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#define CP0SRSMap_SSV1 4
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#define CP0SRSMap_SSV0 0
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int32_t CP0_Cause;
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#define CP0Ca_BD 31
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#define CP0Ca_TI 30
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@ -219,13 +372,14 @@ struct CPUMIPSState {
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#define CP0C3_TL 0
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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/* XXX: Maybe make LLAddr per-TC? */
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target_ulong CP0_LLAddr;
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target_ulong CP0_WatchLo[8];
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int32_t CP0_WatchHi[8];
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target_ulong CP0_XContext;
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int32_t CP0_Framemask;
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int32_t CP0_Debug;
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#define CPDB_DBD 31
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#define CP0DB_DBD 31
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#define CP0DB_DM 30
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#define CP0DB_LSNM 28
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#define CP0DB_Doze 27
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@ -243,6 +397,7 @@ struct CPUMIPSState {
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#define CP0DB_DDBL 2
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#define CP0DB_DBp 1
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#define CP0DB_DSS 0
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int32_t CP0_Debug_tcstatus[MIPS_TC_MAX];
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target_ulong CP0_DEPC;
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int32_t CP0_Performance0;
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int32_t CP0_TagLo;
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@ -284,7 +439,8 @@ struct CPUMIPSState {
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int SYNCI_Step; /* Address step size for SYNCI */
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int CCRes; /* Cycle count resolution/divisor */
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int Status_rw_bitmask; /* Read/write bits in CP0_Status */
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uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
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uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
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#ifdef CONFIG_USER_ONLY
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target_ulong tls_value;
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@ -376,6 +532,7 @@ enum {
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EXCP_TLBS,
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EXCP_DBE,
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EXCP_DDBL,
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EXCP_THREAD,
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EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
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/* may change privilege level */
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EXCP_BRANCH = 0x108, /* branch instruction */
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