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sifive_u: Connect the SiFive PWM device

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Connect the SiFive PWM device and expose it via the device tree.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 22f98648b4e012f78529a56f5ca60b0b27852a4d.1631159656.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-09-09 13:55:15 +10:00
parent 5bf6f1acdd
commit ea6eaa0604
4 changed files with 69 additions and 2 deletions
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14
include/hw/riscv/sifive_u.h
View file

@ -27,6 +27,7 @@
#include "hw/misc/sifive_u_otp.h"
#include "hw/misc/sifive_u_prci.h"
#include "hw/ssi/sifive_spi.h"
#include "hw/timer/sifive_pwm.h"
#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
#define RISCV_U_SOC(obj) \
@ -49,6 +50,7 @@ typedef struct SiFiveUSoCState {
SiFiveSPIState spi0;
SiFiveSPIState spi2;
CadenceGEMState gem;
SiFivePwmState pwm[2];
uint32_t serial;
char *cpu_type;
@ -92,7 +94,9 @@ enum {
SIFIVE_U_DEV_FLASH0,
SIFIVE_U_DEV_DRAM,
SIFIVE_U_DEV_GEM,
SIFIVE_U_DEV_GEM_MGMT
SIFIVE_U_DEV_GEM_MGMT,
SIFIVE_U_DEV_PWM0,
SIFIVE_U_DEV_PWM1
};
enum {
@ -126,6 +130,14 @@ enum {
SIFIVE_U_PDMA_IRQ5 = 28,
SIFIVE_U_PDMA_IRQ6 = 29,
SIFIVE_U_PDMA_IRQ7 = 30,
SIFIVE_U_PWM0_IRQ0 = 42,
SIFIVE_U_PWM0_IRQ1 = 43,
SIFIVE_U_PWM0_IRQ2 = 44,
SIFIVE_U_PWM0_IRQ3 = 45,
SIFIVE_U_PWM1_IRQ0 = 46,
SIFIVE_U_PWM1_IRQ1 = 47,
SIFIVE_U_PWM1_IRQ2 = 48,
SIFIVE_U_PWM1_IRQ3 = 49,
SIFIVE_U_QSPI0_IRQ = 51,
SIFIVE_U_GEM_IRQ = 53
};