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sdhci: implement the Host Control 2 register (tuning sequence)
[based on a patch from Alistair Francis <alistair.francis@xilinx.com> from qemu/xilinx tag xilinx-v2015.2] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-Id: <20180208164818.7961-20-f4bug@amsat.org>
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parent
06c5120b09
commit
ea55a221bf
3 changed files with 30 additions and 3 deletions
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@ -408,14 +408,29 @@ static void sdhci_end_transfer(SDHCIState *s)
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static void sdhci_read_block_from_card(SDHCIState *s)
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{
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int index = 0;
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uint8_t data;
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const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
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if ((s->trnmod & SDHC_TRNS_MULTI) &&
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(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
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return;
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}
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for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
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s->fifo_buffer[index] = sdbus_read_data(&s->sdbus);
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for (index = 0; index < blk_size; index++) {
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data = sdbus_read_data(&s->sdbus);
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if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
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/* Device is not in tunning */
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s->fifo_buffer[index] = data;
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}
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}
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if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
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/* Device is in tunning */
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s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
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s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
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s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
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SDHC_DATA_INHIBIT);
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goto read_done;
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}
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/* New data now available for READ through Buffer Port Register */
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@ -440,6 +455,7 @@ static void sdhci_read_block_from_card(SDHCIState *s)
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}
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}
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read_done:
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sdhci_update_irq(s);
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}
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@ -1005,7 +1021,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size)
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ret = s->norintsigen | (s->errintsigen << 16);
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break;
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case SDHC_ACMD12ERRSTS:
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ret = s->acmd12errsts;
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ret = s->acmd12errsts | (s->hostctl2 << 16);
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break;
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case SDHC_CAPAB:
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ret = (uint32_t)s->capareg;
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