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target-arm queue:

Browse source 
* target/arm: Cleanup and refactoring preparatory to SVE2
  * armsse: Define ARMSSEClass correctly
  * hw/misc/unimp: Improve information provided in log messages
  * hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
  * hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
  * hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
  * hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
  * target/arm: Fill in the WnR syndrome bit in mte_check_fail
  * target/arm: Clarify HCR_EL2 ARMCPRegInfo type
  * hw/arm/musicpal: Use AddressSpace for DMA transfers
  * hw/clock: Minor cleanups
  * hw/arm/sbsa-ref: fix typo breaking PCIe IRQs
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828' into staging

target-arm queue:
 * target/arm: Cleanup and refactoring preparatory to SVE2
 * armsse: Define ARMSSEClass correctly
 * hw/misc/unimp: Improve information provided in log messages
 * hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize
 * hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize
 * hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers
 * hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers
 * target/arm: Fill in the WnR syndrome bit in mte_check_fail
 * target/arm: Clarify HCR_EL2 ARMCPRegInfo type
 * hw/arm/musicpal: Use AddressSpace for DMA transfers
 * hw/clock: Minor cleanups
 * hw/arm/sbsa-ref: fix typo breaking PCIe IRQs

# gpg: Signature made Fri 28 Aug 2020 10:23:02 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200828: (35 commits)
  target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd
  target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd
  target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
  target/arm: Generalize inl_qrdmlah_* helper functions
  target/arm: Tidy SVE tszimm shift formats
  target/arm: Split out gen_gvec_ool_zz
  target/arm: Split out gen_gvec_ool_zzz
  target/arm: Split out gen_gvec_ool_zzp
  target/arm: Merge helper_sve_clr_* and helper_sve_movz_*
  target/arm: Split out gen_gvec_ool_zzzp
  target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
  target/arm: Clean up 4-operand predicate expansion
  target/arm: Merge do_vector2_p into do_mov_p
  target/arm: Rearrange {sve,fp}_check_access assert
  target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn
  target/arm: Split out gen_gvec_fn_zz
  qemu/int128: Add int128_lshift
  armsse: Define ARMSSEClass correctly
  hw/misc/unimp: Display the offset with width of the region size
  hw/misc/unimp: Display the value with width of the access size
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2020-08-28 15:14:40 +01:00
commit ea1bb830cb
29 changed files with 629 additions and 495 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/arm/allwinner-a10.c
View file

@ -155,6 +155,8 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
}
/* SD/MMC */
object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
OBJECT(get_system_memory()), &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, 32));

4
hw/arm/allwinner-h3.c
View file

@ -349,6 +349,8 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);
/* SD/MMC */
object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
OBJECT(get_system_memory()), &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
@ -363,6 +365,8 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
object_property_set_link(OBJECT(&s->emac), "dma-memory",
OBJECT(get_system_memory()), &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,

1
hw/arm/armsse.c
View file

@ -1160,6 +1160,7 @@ static const TypeInfo armsse_info = {
.name = TYPE_ARM_SSE,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ARMSSE),
.class_size = sizeof(ARMSSEClass),
.instance_init = armsse_init,
.abstract = true,
.interfaces = (InterfaceInfo[]) {

45
hw/arm/musicpal.c
View file

@ -30,6 +30,7 @@
#include "hw/audio/wm8750.h"
#include "sysemu/block-backend.h"
#include "sysemu/runstate.h"
#include "sysemu/dma.h"
#include "exec/address-spaces.h"
#include "ui/pixel_ops.h"
#include "qemu/cutils.h"
@ -163,6 +164,8 @@ typedef struct mv88w8618_eth_state {
MemoryRegion iomem;
qemu_irq irq;
MemoryRegion *dma_mr;
AddressSpace dma_as;
uint32_t smir;
uint32_t icr;
uint32_t imr;
@ -176,19 +179,21 @@ typedef struct mv88w8618_eth_state {
NICConf conf;
} mv88w8618_eth_state;
static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
static void eth_rx_desc_put(AddressSpace *dma_as, uint32_t addr,
mv88w8618_rx_desc *desc)
{
cpu_to_le32s(&desc->cmdstat);
cpu_to_le16s(&desc->bytes);
cpu_to_le16s(&desc->buffer_size);
cpu_to_le32s(&desc->buffer);
cpu_to_le32s(&desc->next);
cpu_physical_memory_write(addr, desc, sizeof(*desc));
dma_memory_write(dma_as, addr, desc, sizeof(*desc));
}
static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
static void eth_rx_desc_get(AddressSpace *dma_as, uint32_t addr,
mv88w8618_rx_desc *desc)
{
cpu_physical_memory_read(addr, desc, sizeof(*desc));
dma_memory_read(dma_as, addr, desc, sizeof(*desc));
le32_to_cpus(&desc->cmdstat);
le16_to_cpus(&desc->bytes);
le16_to_cpus(&desc->buffer_size);
@ -209,9 +214,9 @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
continue;
}
do {
eth_rx_desc_get(desc_addr, &desc);
eth_rx_desc_get(&s->dma_as, desc_addr, &desc);
if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
cpu_physical_memory_write(desc.buffer + s->vlan_header,
dma_memory_write(&s->dma_as, desc.buffer + s->vlan_header,
buf, size);
desc.bytes = size + s->vlan_header;
desc.cmdstat &= ~MP_ETH_RX_OWN;
@ -221,7 +226,7 @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
if (s->icr & s->imr) {
qemu_irq_raise(s->irq);
}
eth_rx_desc_put(desc_addr, &desc);
eth_rx_desc_put(&s->dma_as, desc_addr, &desc);
return size;
}
desc_addr = desc.next;
@ -230,19 +235,21 @@ static ssize_t eth_receive(NetClientState *nc, const uint8_t *buf, size_t size)
return size;
}
static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
static void eth_tx_desc_put(AddressSpace *dma_as, uint32_t addr,
mv88w8618_tx_desc *desc)
{
cpu_to_le32s(&desc->cmdstat);
cpu_to_le16s(&desc->res);
cpu_to_le16s(&desc->bytes);
cpu_to_le32s(&desc->buffer);
cpu_to_le32s(&desc->next);
cpu_physical_memory_write(addr, desc, sizeof(*desc));
dma_memory_write(dma_as, addr, desc, sizeof(*desc));
}
static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
static void eth_tx_desc_get(AddressSpace *dma_as, uint32_t addr,
mv88w8618_tx_desc *desc)
{
cpu_physical_memory_read(addr, desc, sizeof(*desc));
dma_memory_read(dma_as, addr, desc, sizeof(*desc));
le32_to_cpus(&desc->cmdstat);
le16_to_cpus(&desc->res);
le16_to_cpus(&desc->bytes);
@ -259,17 +266,17 @@ static void eth_send(mv88w8618_eth_state *s, int queue_index)
int len;
do {
eth_tx_desc_get(desc_addr, &desc);
eth_tx_desc_get(&s->dma_as, desc_addr, &desc);
next_desc = desc.next;
if (desc.cmdstat & MP_ETH_TX_OWN) {
len = desc.bytes;
if (len < 2048) {
cpu_physical_memory_read(desc.buffer, buf, len);
dma_memory_read(&s->dma_as, desc.buffer, buf, len);
qemu_send_packet(qemu_get_queue(s->nic), buf, len);
}
desc.cmdstat &= ~MP_ETH_TX_OWN;
s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
eth_tx_desc_put(desc_addr, &desc);
eth_tx_desc_put(&s->dma_as, desc_addr, &desc);
}
desc_addr = next_desc;
} while (desc_addr != s->tx_queue[queue_index]);
@ -405,6 +412,12 @@ static void mv88w8618_eth_realize(DeviceState *dev, Error **errp)
{
mv88w8618_eth_state *s = MV88W8618_ETH(dev);
if (!s->dma_mr) {
error_setg(errp, TYPE_MV88W8618_ETH " 'dma-memory' link not set");
return;
}
address_space_init(&s->dma_as, s->dma_mr, "emac-dma");
s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id, s);
}
@ -428,6 +441,8 @@ static const VMStateDescription mv88w8618_eth_vmsd = {
static Property mv88w8618_eth_properties[] = {
DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
DEFINE_PROP_LINK("dma-memory", mv88w8618_eth_state, dma_mr,
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_END_OF_LIST(),
};
@ -1653,6 +1668,8 @@ static void musicpal_init(MachineState *machine)
qemu_check_nic_model(&nd_table[0], "mv88w8618");
dev = qdev_new(TYPE_MV88W8618_ETH);
qdev_set_nic_properties(dev, &nd_table[0]);
object_property_set_link(OBJECT(dev), "dma-memory",
OBJECT(get_system_memory()), &error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, MP_ETH_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[MP_ETH_IRQ]);

2
hw/arm/sbsa-ref.c
View file

@ -554,7 +554,7 @@ static void create_pcie(SBSAMachineState *sms)
for (i = 0; i < GPEX_NUM_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
qdev_get_gpio_in(sms->gic, irq + 1));
qdev_get_gpio_in(sms->gic, irq + i));
gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
}

24
hw/arm/xilinx_zynq.c
View file

@ -222,18 +222,18 @@ static void zynq_init(MachineState *machine)
1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
0);
/* Create slcr, keep a pointer to connect clocks */
slcr = qdev_new("xilinx,zynq_slcr");
sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
/* Create the main clock source, and feed slcr with it */
zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK));
object_property_add_child(OBJECT(zynq_machine), "ps_clk",
OBJECT(zynq_machine->ps_clk));
object_unref(OBJECT(zynq_machine->ps_clk));
clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY);
/* Create slcr, keep a pointer to connect clocks */
slcr = qdev_new("xilinx,zynq_slcr");
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
dev = qdev_new(TYPE_A9MPCORE_PRIV);
qdev_prop_set_uint32(dev, "num-cpu", 1);
@ -254,12 +254,22 @@ static void zynq_init(MachineState *machine)
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]);
sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]);
dev = cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
dev = qdev_new(TYPE_CADENCE_UART);
busdev = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
qdev_connect_clock_in(dev, "refclk",
qdev_get_clock_out(slcr, "uart0_ref_clk"));
dev = cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xE0000000);
sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]);
dev = qdev_new(TYPE_CADENCE_UART);
busdev = SYS_BUS_DEVICE(dev);
qdev_prop_set_chr(dev, "chardev", serial_hd(1));
qdev_connect_clock_in(dev, "refclk",
qdev_get_clock_out(slcr, "uart1_ref_clk"));
sysbus_realize_and_unref(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, 0xE0001000);
sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]);
sysbus_create_varargs("cadence_ttc", 0xF8001000,
pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);