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https://github.com/Motorhead1991/qemu.git
synced 2025-08-04 16:23:55 -06:00
Fix miscellaneous display warnings for PowerPC & alpha targets
and parallel CFI flash driver. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2661 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
ba13c4327e
commit
e96efcfcb1
8 changed files with 46 additions and 31 deletions
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@ -91,7 +91,7 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
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uint32_t ret;
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uint8_t *p;
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DPRINTF("%s: offset %08x\n", __func__, offset);
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DPRINTF("%s: offset " TARGET_FMT_lx "\n", __func__, offset);
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ret = -1;
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offset -= pfl->base;
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boff = offset & 0xFF;
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@ -161,7 +161,7 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
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default:
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goto flash_read;
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}
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DPRINTF("%s: ID %d %x\n", __func__, boff, ret);
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DPRINTF("%s: ID " TARGET_FMT_ld " %x\n", __func__, boff, ret);
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break;
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case 0xA0:
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case 0x10:
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@ -214,7 +214,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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offset -= pfl->base;
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cmd = value;
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DPRINTF("%s: offset %08x %08x %d\n", __func__, offset, value, width);
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DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d\n", __func__,
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offset, value, width);
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if (pfl->cmd != 0xA0 && cmd == 0xF0) {
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DPRINTF("%s: flash reset asked (%02x %02x)\n",
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__func__, pfl->cmd, cmd);
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@ -239,7 +240,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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return;
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}
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if (boff != 0x555 || cmd != 0xAA) {
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DPRINTF("%s: unlock0 failed %04x %02x %04x\n",
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DPRINTF("%s: unlock0 failed " TARGET_FMT_lx " %02x %04x\n",
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__func__, boff, cmd, 0x555);
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goto reset_flash;
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}
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@ -249,7 +250,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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/* We started an unlock sequence */
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check_unlock1:
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if (boff != 0x2AA || cmd != 0x55) {
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DPRINTF("%s: unlock1 failed %04x %02x\n", __func__, boff, cmd);
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DPRINTF("%s: unlock1 failed " TARGET_FMT_lx " %02x\n", __func__,
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boff, cmd);
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goto reset_flash;
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}
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DPRINTF("%s: unlock sequence done\n", __func__);
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@ -257,7 +259,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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case 2:
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/* We finished an unlock sequence */
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if (!pfl->bypass && boff != 0x555) {
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DPRINTF("%s: command failed %04x %02x\n", __func__, boff, cmd);
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DPRINTF("%s: command failed " TARGET_FMT_lx " %02x\n", __func__,
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boff, cmd);
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goto reset_flash;
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}
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switch (cmd) {
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@ -281,7 +284,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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/* We need another unlock sequence */
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goto check_unlock0;
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case 0xA0:
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DPRINTF("%s: write data offset %08x %08x %d\n",
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DPRINTF("%s: write data offset " TARGET_FMT_lx " %08x %d\n",
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__func__, offset, value, width);
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p = pfl->storage;
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switch (width) {
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@ -352,7 +355,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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switch (cmd) {
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case 0x10:
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if (boff != 0x555) {
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DPRINTF("%s: chip erase: invalid address %04x\n",
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DPRINTF("%s: chip erase: invalid address " TARGET_FMT_lx "\n",
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__func__, offset);
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goto reset_flash;
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}
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@ -369,7 +372,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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/* Sector erase */
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p = pfl->storage;
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offset &= ~(pfl->sector_len - 1);
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DPRINTF("%s: start sector erase at %08x\n", __func__, offset);
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DPRINTF("%s: start sector erase at " TARGET_FMT_lx "\n", __func__,
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offset);
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memset(p + offset, 0xFF, pfl->sector_len);
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pflash_update(pfl, offset, pfl->sector_len);
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pfl->status = 0x00;
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15
hw/ppc.c
15
hw/ppc.c
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@ -464,8 +464,8 @@ static void cpu_4xx_fit_cb (void *opaque)
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if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
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ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
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if (loglevel) {
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fprintf(logfile, "%s: ir %d TCR %08x TSR %08x\n", __func__,
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(env->spr[SPR_40x_TCR] >> 23) & 0x1,
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fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
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(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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}
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}
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@ -495,9 +495,10 @@ static void cpu_4xx_pit_cb (void *opaque)
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if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
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ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
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if (loglevel) {
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fprintf(logfile, "%s: ar %d ir %d TCR %08x TSR %08x %08lx\n", __func__,
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(env->spr[SPR_40x_TCR] >> 22) & 0x1,
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(env->spr[SPR_40x_TCR] >> 26) & 0x1,
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fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
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"%016" PRIx64 "\n", __func__,
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(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
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(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
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ppcemb_timer->pit_reload);
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}
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@ -536,7 +537,7 @@ static void cpu_4xx_wdt_cb (void *opaque)
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if (next == now)
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next++;
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if (loglevel) {
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fprintf(logfile, "%s: TCR %08x TSR %08x\n", __func__,
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fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
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env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
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}
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switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
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@ -587,7 +588,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
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qemu_del_timer(tb_env->decr_timer);
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} else {
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if (loglevel)
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fprintf(logfile, "%s: start PIT 0x%08x\n", __func__, val);
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fprintf(logfile, "%s: start PIT 0x" ADDRX "\n", __func__, val);
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now = qemu_get_clock(vm_clock);
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next = now + muldiv64(val, ticks_per_sec, tb_env->tb_freq);
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if (next == now)
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@ -48,7 +48,7 @@ static int macio_nvram_mem_index = -1;
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static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
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printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
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}
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static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
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@ -61,7 +61,7 @@ static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
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{
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printf("%s: 0x%08x => 0x00000000\n", __func__, addr);
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printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
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return 0;
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}
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@ -261,7 +261,7 @@ static int vga_osi_call(CPUState *env)
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/* R6 = x, R7 = y, R8 = visible, R9 = data */
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break;
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default:
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fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]);
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fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
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break;
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}
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return 1; /* osi_call handled */
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