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target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'

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accel/tcg/ files requires the following definitions:

  - TARGET_LONG_BITS
  - TARGET_PAGE_BITS
  - TARGET_PHYS_ADDR_SPACE_BITS
  - TCG_GUEST_DEFAULT_MO

The first 3 are defined in "cpu-param.h". The last one
in "cpu.h", with a bunch of definitions irrelevant for
TCG. By moving the TCG_GUEST_DEFAULT_MO definition to
"cpu-param.h", we can simplify various accel/tcg includes.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20231211212003.21686-4-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-12-05 14:31:59 +01:00
parent 83fb360d6a
commit e92dd33224
28 changed files with 66 additions and 62 deletions
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8
target/hppa/cpu-param.h
View file

@ -21,4 +21,12 @@
#define TARGET_PAGE_BITS 12
/* PA-RISC 1.x processors have a strong memory model. */
/*
* ??? While we do not yet implement PA-RISC 2.0, those processors have
* a weak memory model, but with TLB bits that force ordering on a per-page
* basis. It's probably easier to fall back to a strong memory model.
*/
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif

6
target/hppa/cpu.h
View file

@ -25,12 +25,6 @@
#include "qemu/cpu-float.h"
#include "qemu/interval-tree.h"
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
a weak memory model, but with TLB bits that force ordering on a per-page
basis. It's probably easier to fall back to a strong memory model. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#define MMU_ABS_W_IDX 6
#define MMU_ABS_IDX 7
#define MMU_KERNEL_IDX 8