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target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
TLB needn't be flushed when pmpcfg/pmpaddr don't changes. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-Id: <20230517091519.34439-11-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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parent
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commit
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1 changed files with 18 additions and 10 deletions
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@ -26,7 +26,7 @@
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#include "trace.h"
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#include "trace.h"
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
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static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
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uint8_t val);
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uint8_t val);
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static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
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static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
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static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
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static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
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@ -83,7 +83,7 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
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* Accessor to set the cfg reg for a specific PMP/HART
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* Accessor to set the cfg reg for a specific PMP/HART
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* Bounds checks and relevant lock bit.
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* Bounds checks and relevant lock bit.
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*/
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*/
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static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
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static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
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{
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{
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if (pmp_index < MAX_RISCV_PMPS) {
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if (pmp_index < MAX_RISCV_PMPS) {
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bool locked = true;
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bool locked = true;
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@ -119,14 +119,17 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
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if (locked) {
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if (locked) {
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qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
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qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
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} else {
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} else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
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env->pmp_state.pmp[pmp_index].cfg_reg = val;
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env->pmp_state.pmp[pmp_index].cfg_reg = val;
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pmp_update_rule(env, pmp_index);
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pmp_update_rule(env, pmp_index);
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return true;
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}
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}
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} else {
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpcfg write - out of bounds\n");
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"ignoring pmpcfg write - out of bounds\n");
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}
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}
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return false;
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}
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}
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static void pmp_decode_napot(target_ulong a, target_ulong *sa,
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static void pmp_decode_napot(target_ulong a, target_ulong *sa,
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@ -467,16 +470,19 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
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int i;
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int i;
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uint8_t cfg_val;
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uint8_t cfg_val;
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int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
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int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
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bool modified = false;
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trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
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trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
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for (i = 0; i < pmpcfg_nums; i++) {
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for (i = 0; i < pmpcfg_nums; i++) {
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cfg_val = (val >> 8 * i) & 0xff;
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cfg_val = (val >> 8 * i) & 0xff;
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pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
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modified |= pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
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}
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}
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/* If PMP permission of any addr has been changed, flush TLB pages. */
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/* If PMP permission of any addr has been changed, flush TLB pages. */
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tlb_flush(env_cpu(env));
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if (modified) {
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tlb_flush(env_cpu(env));
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}
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}
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}
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@ -526,12 +532,14 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
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}
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}
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if (!pmp_is_locked(env, addr_index)) {
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if (!pmp_is_locked(env, addr_index)) {
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env->pmp_state.pmp[addr_index].addr_reg = val;
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if (env->pmp_state.pmp[addr_index].addr_reg != val) {
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pmp_update_rule_addr(env, addr_index);
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env->pmp_state.pmp[addr_index].addr_reg = val;
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if (is_next_cfg_tor) {
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pmp_update_rule_addr(env, addr_index);
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pmp_update_rule_addr(env, addr_index + 1);
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if (is_next_cfg_tor) {
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pmp_update_rule_addr(env, addr_index + 1);
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}
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tlb_flush(env_cpu(env));
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}
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}
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tlb_flush(env_cpu(env));
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} else {
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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qemu_log_mask(LOG_GUEST_ERROR,
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"ignoring pmpaddr write - locked\n");
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"ignoring pmpaddr write - locked\n");
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