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hw/intc: Add RISC-V AIA APLIC device emulation

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The RISC-V AIA (Advanced Interrupt Architecture) defines a new
interrupt controller for wired interrupts called APLIC (Advanced
Platform Level Interrupt Controller). The APLIC is capabable of
forwarding wired interupts to RISC-V HARTs directly or as MSIs
(Message Signaled Interupts).

This patch adds device emulation for RISC-V AIA APLIC.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-19-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel 2022-02-04 23:16:54 +05:30 • committed by Alistair Francis
parent 91870b510a
commit e8f79343cf
4 changed files with 1061 additions and 0 deletions
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79
include/hw/intc/riscv_aplic.h Normal file
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/*
* RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface
*
* Copyright (c) 2021 Western Digital Corporation or its affiliates.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_RISCV_APLIC_H
#define HW_RISCV_APLIC_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_RISCV_APLIC "riscv.aplic"
typedef struct RISCVAPLICState RISCVAPLICState;
DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC)
#define APLIC_MIN_SIZE 0x4000
#define APLIC_SIZE_ALIGN(__x) (((__x) + (APLIC_MIN_SIZE - 1)) & \
~(APLIC_MIN_SIZE - 1))
#define APLIC_SIZE(__num_harts) (APLIC_MIN_SIZE + \
APLIC_SIZE_ALIGN(32 * (__num_harts)))
struct RISCVAPLICState {
/*< private >*/
SysBusDevice parent_obj;
qemu_irq *external_irqs;
/*< public >*/
MemoryRegion mmio;
uint32_t bitfield_words;
uint32_t domaincfg;
uint32_t mmsicfgaddr;
uint32_t mmsicfgaddrH;
uint32_t smsicfgaddr;
uint32_t smsicfgaddrH;
uint32_t genmsi;
uint32_t *sourcecfg;
uint32_t *state;
uint32_t *target;
uint32_t *idelivery;
uint32_t *iforce;
uint32_t *ithreshold;
/* topology */
#define QEMU_APLIC_MAX_CHILDREN 16
struct RISCVAPLICState *parent;
struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN];
uint16_t num_children;
/* config */
uint32_t aperture_size;
uint32_t hartid_base;
uint32_t num_harts;
uint32_t iprio_mask;
uint32_t num_irqs;
bool msimode;
bool mmode;
};
void riscv_aplic_add_child(DeviceState *parent, DeviceState *child);
DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size,
uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources,
uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent);
#endif