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hw/riscv/virt: Update GPEX MMIO related properties

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Update the GPEX host bridge properties related to MMIO ranges with
values set for the virt machine.

Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20231218150247.466427-12-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Sunil V L 2023-12-18 20:32:45 +05:30 • committed by Alistair Francis
parent 8f6a487488
commit e86e95270e
2 changed files with 33 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

47
hw/riscv/virt.c
View file

@ -1054,21 +1054,45 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap)
} }
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
hwaddr ecam_base, hwaddr ecam_size, DeviceState *irqchip,
hwaddr mmio_base, hwaddr mmio_size, RISCVVirtState *s)
hwaddr high_mmio_base,
hwaddr high_mmio_size,
hwaddr pio_base,
DeviceState *irqchip)
{ {
DeviceState *dev; DeviceState *dev;
MemoryRegion *ecam_alias, *ecam_reg; MemoryRegion *ecam_alias, *ecam_reg;
MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
hwaddr ecam_base = s->memmap[VIRT_PCIE_ECAM].base;
hwaddr ecam_size = s->memmap[VIRT_PCIE_ECAM].size;
hwaddr mmio_base = s->memmap[VIRT_PCIE_MMIO].base;
hwaddr mmio_size = s->memmap[VIRT_PCIE_MMIO].size;
hwaddr high_mmio_base = virt_high_pcie_memmap.base;
hwaddr high_mmio_size = virt_high_pcie_memmap.size;
hwaddr pio_base = s->memmap[VIRT_PCIE_PIO].base;
hwaddr pio_size = s->memmap[VIRT_PCIE_PIO].size;
qemu_irq irq; qemu_irq irq;
int i; int i;
dev = qdev_new(TYPE_GPEX_HOST); dev = qdev_new(TYPE_GPEX_HOST);
/* Set GPEX object properties for the virt machine */
object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_BASE,
ecam_base, NULL);
object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ECAM_SIZE,
ecam_size, NULL);
object_property_set_uint(OBJECT(GPEX_HOST(dev)),
PCI_HOST_BELOW_4G_MMIO_BASE,
mmio_base, NULL);
object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_BELOW_4G_MMIO_SIZE,
mmio_size, NULL);
object_property_set_uint(OBJECT(GPEX_HOST(dev)),
PCI_HOST_ABOVE_4G_MMIO_BASE,
high_mmio_base, NULL);
object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_ABOVE_4G_MMIO_SIZE,
high_mmio_size, NULL);
object_property_set_uint(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_BASE,
pio_base, NULL);
object_property_set_int(OBJECT(GPEX_HOST(dev)), PCI_HOST_PIO_SIZE,
pio_size, NULL);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ecam_alias = g_new0(MemoryRegion, 1); ecam_alias = g_new0(MemoryRegion, 1);
@ -1099,6 +1123,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
} }
GPEX_HOST(dev)->gpex_cfg.bus = PCI_HOST_BRIDGE(GPEX_HOST(dev))->bus;
return dev; return dev;
} }
@ -1494,15 +1519,7 @@ static void virt_machine_init(MachineState *machine)
qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i)); qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
} }
gpex_pcie_init(system_memory, gpex_pcie_init(system_memory, pcie_irqchip, s);
memmap[VIRT_PCIE_ECAM].base,
memmap[VIRT_PCIE_ECAM].size,
memmap[VIRT_PCIE_MMIO].base,
memmap[VIRT_PCIE_MMIO].size,
virt_high_pcie_memmap.base,
virt_high_pcie_memmap.size,
memmap[VIRT_PCIE_PIO].base,
pcie_irqchip);
create_platform_bus(s, mmio_irqchip); create_platform_bus(s, mmio_irqchip);

1
include/hw/riscv/virt.h
View file

@ -61,6 +61,7 @@ struct RISCVVirtState {
char *oem_table_id; char *oem_table_id;
OnOffAuto acpi; OnOffAuto acpi;
const MemMapEntry *memmap; const MemMapEntry *memmap;
struct GPEXHost *gpex_host;
}; };
enum { enum {