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SPARC merge
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1179 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
parent
9772c73bbc
commit
e80cfcfc88
37 changed files with 4507 additions and 1155 deletions
35
hw/fdc.c
35
hw/fdc.c
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@ -21,6 +21,10 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*
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* The controller is used in Sun4m systems in a slightly different
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* way. There are changes in DOR register and DMA is not available.
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*/
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#include "vl.h"
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/********************************************************/
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@ -90,6 +94,16 @@ typedef struct fdrive_t {
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uint8_t ro; /* Is read-only */
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} fdrive_t;
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#ifdef TARGET_SPARC
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#define DMA_read_memory(a,b,c,d)
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#define DMA_write_memory(a,b,c,d)
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#define DMA_register_channel(a,b,c)
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#define DMA_hold_DREQ(a)
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#define DMA_release_DREQ(a)
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#define DMA_get_channel_mode(a) (0)
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#define DMA_schedule(a)
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#endif
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static void fd_init (fdrive_t *drv, BlockDriverState *bs)
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{
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/* Drive */
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@ -455,6 +469,18 @@ static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
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}
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}
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static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
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fdctrl_read,
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fdctrl_read,
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fdctrl_read,
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};
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static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
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fdctrl_write,
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fdctrl_write,
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fdctrl_write,
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};
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static void fd_change_cb (void *opaque)
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{
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fdrive_t *drv = opaque;
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@ -473,7 +499,7 @@ fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
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BlockDriverState **fds)
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{
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fdctrl_t *fdctrl;
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// int io_mem;
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int io_mem;
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int i;
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FLOPPY_DPRINTF("init controller\n");
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@ -504,11 +530,8 @@ fdctrl_t *fdctrl_init (int irq_lvl, int dma_chann, int mem_mapped,
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fdctrl_reset(fdctrl, 0);
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fdctrl->state = FD_CTRL_ACTIVE;
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if (mem_mapped) {
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FLOPPY_ERROR("memory mapped floppy not supported by now !\n");
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#if 0
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io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write);
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cpu_register_physical_memory(base, 0x08, io_mem);
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#endif
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io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write, fdctrl);
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cpu_register_physical_memory(io_base, 0x08, io_mem);
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} else {
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register_ioport_read(io_base + 0x01, 5, 1, &fdctrl_read, fdctrl);
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register_ioport_read(io_base + 0x07, 1, 1, &fdctrl_read, fdctrl);
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