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ppc/ppc405: Remove boards
The ref405ep machine is the only PPC 405 machine. Drop all support by removing the SoC and associated devices as-well as the machine. Link: https://lore.kernel.org/qemu-devel/20250110141800.1587589-3-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20250204080649.836155-3-clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Cédric Le Goater
Nicholas Piggin
parent
e5029e28f0
commit
e7dba30e82
9 changed files with 7 additions and 1949 deletions
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@ -1407,12 +1407,6 @@ F: hw/openrisc/openrisc_sim.c
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PowerPC Machines
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PowerPC Machines
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----------------
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----------------
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405 (ref405ep)
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L: qemu-ppc@nongnu.org
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S: Orphan
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F: hw/ppc/ppc405*
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F: tests/functional/test_ppc_405.py
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Bamboo
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Bamboo
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L: qemu-ppc@nongnu.org
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L: qemu-ppc@nongnu.org
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S: Orphan
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S: Orphan
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@ -277,14 +277,6 @@ deprecated; use the new name ``dtb-randomness`` instead. The new name
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better reflects the way this property affects all random data within
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better reflects the way this property affects all random data within
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the device tree blob, not just the ``kaslr-seed`` node.
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the device tree blob, not just the ``kaslr-seed`` node.
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PPC 405 ``ref405ep`` machine (since 9.1)
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''''''''''''''''''''''''''''''''''''''''
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The ``ref405ep`` machine and PPC 405 CPU have no known users, firmware
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images are not available, OpenWRT dropped support in 2019, U-Boot in
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2017, Linux also is dropping support in 2024. It is time to let go of
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this ancient hardware and focus on newer CPUs and platforms.
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Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
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Big-Endian variants of MicroBlaze ``petalogix-ml605`` and ``xlnx-zynqmp-pmu`` machines (since 9.2)
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''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
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''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
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@ -1064,6 +1064,13 @@ for all machine types using the PXA2xx and OMAP2 SoCs. We are also
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dropping the ``cheetah`` OMAP1 board, because we don't have any
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dropping the ``cheetah`` OMAP1 board, because we don't have any
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test images for it and don't know of anybody who does.
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test images for it and don't know of anybody who does.
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ppc ``ref405ep`` machine (removed in 10.0)
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''''''''''''''''''''''''''''''''''''''''''
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This machine was removed because PPC 405 CPU have no known users,
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firmware images are not available, OpenWRT dropped support in 2019,
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U-Boot in 2017, and Linux in 2024.
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linux-user mode CPUs
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linux-user mode CPUs
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--------------------
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--------------------
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@ -4,6 +4,5 @@ Embedded family boards
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- ``bamboo`` bamboo
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- ``bamboo`` bamboo
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- ``mpc8544ds`` mpc8544ds
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- ``mpc8544ds`` mpc8544ds
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- ``ppce500`` generic paravirt e500 platform
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- ``ppce500`` generic paravirt e500 platform
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- ``ref405ep`` ref405ep
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- ``sam460ex`` aCube Sam460ex
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- ``sam460ex`` aCube Sam460ex
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- ``virtex-ml507`` Xilinx Virtex ML507 reference design
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- ``virtex-ml507`` Xilinx Virtex ML507 reference design
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@ -44,15 +44,6 @@ config POWERNV
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select SSI_M25P80
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select SSI_M25P80
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select PNV_SPI
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select PNV_SPI
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config PPC405
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bool
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default y
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depends on PPC
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select M48T59
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select PFLASH_CFI02
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select PPC4XX
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select SERIAL_MM
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config PPC440
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config PPC440
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bool
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bool
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default y
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default y
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@ -57,9 +57,6 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
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'pnv_n1_chiplet.c',
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'pnv_n1_chiplet.c',
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))
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))
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# PowerPC 4xx boards
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# PowerPC 4xx boards
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ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
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'ppc405_boards.c',
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'ppc405_uc.c'))
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ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
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ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
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'ppc440_bamboo.c',
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'ppc440_bamboo.c',
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'ppc440_uc.c'))
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'ppc440_uc.c'))
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186
hw/ppc/ppc405.h
186
hw/ppc/ppc405.h
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@ -1,186 +0,0 @@
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/*
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* QEMU PowerPC 405 shared definitions
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef PPC405_H
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#define PPC405_H
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#include "qom/object.h"
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#include "hw/ppc/ppc4xx.h"
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#include "hw/intc/ppc-uic.h"
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#include "hw/i2c/ppc4xx_i2c.h"
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/* PLB to OPB bridge */
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#define TYPE_PPC405_POB "ppc405-pob"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
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struct Ppc405PobState {
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Ppc4xxDcrDeviceState parent_obj;
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uint32_t bear;
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uint32_t besr0;
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uint32_t besr1;
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};
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/* OPB arbitrer */
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#define TYPE_PPC405_OPBA "ppc405-opba"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
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struct Ppc405OpbaState {
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SysBusDevice parent_obj;
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MemoryRegion io;
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uint8_t cr;
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uint8_t pr;
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};
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/* DMA controller */
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#define TYPE_PPC405_DMA "ppc405-dma"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
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struct Ppc405DmaState {
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Ppc4xxDcrDeviceState parent_obj;
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qemu_irq irqs[4];
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uint32_t cr[4];
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uint32_t ct[4];
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uint32_t da[4];
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uint32_t sa[4];
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uint32_t sg[4];
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uint32_t sr;
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uint32_t sgc;
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uint32_t slp;
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uint32_t pol;
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};
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/* GPIO */
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#define TYPE_PPC405_GPIO "ppc405-gpio"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GpioState, PPC405_GPIO);
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struct Ppc405GpioState {
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SysBusDevice parent_obj;
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MemoryRegion io;
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uint32_t or;
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uint32_t tcr;
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uint32_t osrh;
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uint32_t osrl;
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uint32_t tsrh;
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uint32_t tsrl;
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uint32_t odr;
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uint32_t ir;
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uint32_t rr1;
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uint32_t isr1h;
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uint32_t isr1l;
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};
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/* On Chip Memory */
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#define TYPE_PPC405_OCM "ppc405-ocm"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM);
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struct Ppc405OcmState {
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Ppc4xxDcrDeviceState parent_obj;
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MemoryRegion ram;
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MemoryRegion isarc_ram;
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MemoryRegion dsarc_ram;
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uint32_t isarc;
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uint32_t isacntl;
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uint32_t dsarc;
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uint32_t dsacntl;
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};
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/* General purpose timers */
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#define TYPE_PPC405_GPT "ppc405-gpt"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT);
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struct Ppc405GptState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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int64_t tb_offset;
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uint32_t tb_freq;
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QEMUTimer *timer;
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qemu_irq irqs[5];
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uint32_t oe;
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uint32_t ol;
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uint32_t im;
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uint32_t is;
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uint32_t ie;
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uint32_t comp[5];
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uint32_t mask[5];
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};
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#define TYPE_PPC405_CPC "ppc405-cpc"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC);
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enum {
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PPC405EP_CPU_CLK = 0,
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PPC405EP_PLB_CLK = 1,
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PPC405EP_OPB_CLK = 2,
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PPC405EP_EBC_CLK = 3,
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PPC405EP_MAL_CLK = 4,
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PPC405EP_PCI_CLK = 5,
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PPC405EP_UART0_CLK = 6,
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PPC405EP_UART1_CLK = 7,
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PPC405EP_CLK_NB = 8,
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};
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struct Ppc405CpcState {
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Ppc4xxDcrDeviceState parent_obj;
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uint32_t sysclk;
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clk_setup_t clk_setup[PPC405EP_CLK_NB];
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uint32_t boot;
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uint32_t epctl;
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uint32_t pllmr[2];
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uint32_t ucr;
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uint32_t srr;
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uint32_t jtagid;
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uint32_t pci;
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/* Clock and power management */
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uint32_t er;
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uint32_t fr;
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uint32_t sr;
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};
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#define TYPE_PPC405_SOC "ppc405-soc"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405SoCState, PPC405_SOC);
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struct Ppc405SoCState {
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/* Private */
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DeviceState parent_obj;
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/* Public */
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PowerPCCPU cpu;
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PPCUIC uic;
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Ppc405CpcState cpc;
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Ppc405GptState gpt;
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Ppc405OcmState ocm;
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Ppc405GpioState gpio;
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Ppc405DmaState dma;
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PPC4xxI2CState i2c;
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Ppc4xxEbcState ebc;
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Ppc405OpbaState opba;
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Ppc405PobState pob;
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Ppc4xxPlbState plb;
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Ppc4xxMalState mal;
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Ppc4xxSdramDdrState sdram;
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};
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#endif /* PPC405_H */
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@ -1,520 +0,0 @@
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/*
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* QEMU PowerPC 405 evaluation boards emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "qemu/datadir.h"
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#include "cpu.h"
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#include "hw/ppc/ppc.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "ppc405.h"
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#include "hw/rtc/m48t59.h"
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#include "hw/block/flash.h"
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#include "system/qtest.h"
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#include "system/reset.h"
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#include "system/block-backend.h"
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#include "hw/boards.h"
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#include "qemu/error-report.h"
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#include "hw/loader.h"
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#include "qemu/cutils.h"
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#include "elf.h"
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#define BIOS_FILENAME "ppc405_rom.bin"
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#define BIOS_SIZE (2 * MiB)
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#define KERNEL_LOAD_ADDR 0x01000000
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#define INITRD_LOAD_ADDR 0x01800000
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#define PPC405EP_SDRAM_BASE 0x00000000
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#define PPC405EP_SRAM_BASE 0xFFF00000
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#define PPC405EP_SRAM_SIZE (512 * KiB)
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#define USE_FLASH_BIOS
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#define TYPE_PPC405_MACHINE MACHINE_TYPE_NAME("ppc405")
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE);
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struct Ppc405MachineState {
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/* Private */
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MachineState parent_obj;
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/* Public */
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Ppc405SoCState soc;
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};
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/* CPU reset handler when booting directly from a loaded kernel */
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static struct boot_info {
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uint32_t entry;
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uint32_t bdloc;
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uint32_t initrd_base;
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uint32_t initrd_size;
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uint32_t cmdline_base;
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uint32_t cmdline_size;
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} boot_info;
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static void main_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
|
|
||||||
struct boot_info *bi = env->load_info;
|
|
||||||
|
|
||||||
cpu_reset(CPU(cpu));
|
|
||||||
|
|
||||||
/* stack: top of sram */
|
|
||||||
env->gpr[1] = PPC405EP_SRAM_BASE + PPC405EP_SRAM_SIZE - 8;
|
|
||||||
|
|
||||||
/* Tune our boot state */
|
|
||||||
env->gpr[3] = bi->bdloc;
|
|
||||||
env->gpr[4] = bi->initrd_base;
|
|
||||||
env->gpr[5] = bi->initrd_base + bi->initrd_size;
|
|
||||||
env->gpr[6] = bi->cmdline_base;
|
|
||||||
env->gpr[7] = bi->cmdline_size;
|
|
||||||
|
|
||||||
env->nip = bi->entry;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Bootinfo as set-up by u-boot */
|
|
||||||
typedef struct {
|
|
||||||
uint32_t bi_memstart;
|
|
||||||
uint32_t bi_memsize;
|
|
||||||
uint32_t bi_flashstart;
|
|
||||||
uint32_t bi_flashsize;
|
|
||||||
uint32_t bi_flashoffset; /* 0x10 */
|
|
||||||
uint32_t bi_sramstart;
|
|
||||||
uint32_t bi_sramsize;
|
|
||||||
uint32_t bi_bootflags;
|
|
||||||
uint32_t bi_ipaddr; /* 0x20 */
|
|
||||||
uint8_t bi_enetaddr[6];
|
|
||||||
uint16_t bi_ethspeed;
|
|
||||||
uint32_t bi_intfreq;
|
|
||||||
uint32_t bi_busfreq; /* 0x30 */
|
|
||||||
uint32_t bi_baudrate;
|
|
||||||
uint8_t bi_s_version[4];
|
|
||||||
uint8_t bi_r_version[32];
|
|
||||||
uint32_t bi_procfreq;
|
|
||||||
uint32_t bi_plb_busfreq;
|
|
||||||
uint32_t bi_pci_busfreq;
|
|
||||||
uint8_t bi_pci_enetaddr[6];
|
|
||||||
uint8_t bi_pci_enetaddr2[6]; /* PPC405EP specific */
|
|
||||||
uint32_t bi_opbfreq;
|
|
||||||
uint32_t bi_iic_fast[2];
|
|
||||||
} ppc4xx_bd_info_t;
|
|
||||||
|
|
||||||
static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd,
|
|
||||||
ram_addr_t ram_size)
|
|
||||||
{
|
|
||||||
memset(bd, 0, sizeof(*bd));
|
|
||||||
|
|
||||||
bd->bi_memstart = PPC405EP_SDRAM_BASE;
|
|
||||||
bd->bi_memsize = ram_size;
|
|
||||||
bd->bi_sramstart = PPC405EP_SRAM_BASE;
|
|
||||||
bd->bi_sramsize = PPC405EP_SRAM_SIZE;
|
|
||||||
bd->bi_bootflags = 0;
|
|
||||||
bd->bi_intfreq = 133333333;
|
|
||||||
bd->bi_busfreq = 33333333;
|
|
||||||
bd->bi_baudrate = 115200;
|
|
||||||
bd->bi_s_version[0] = 'Q';
|
|
||||||
bd->bi_s_version[1] = 'M';
|
|
||||||
bd->bi_s_version[2] = 'U';
|
|
||||||
bd->bi_s_version[3] = '\0';
|
|
||||||
bd->bi_r_version[0] = 'Q';
|
|
||||||
bd->bi_r_version[1] = 'E';
|
|
||||||
bd->bi_r_version[2] = 'M';
|
|
||||||
bd->bi_r_version[3] = 'U';
|
|
||||||
bd->bi_r_version[4] = '\0';
|
|
||||||
bd->bi_procfreq = 133333333;
|
|
||||||
bd->bi_plb_busfreq = 33333333;
|
|
||||||
bd->bi_pci_busfreq = 33333333;
|
|
||||||
bd->bi_opbfreq = 33333333;
|
|
||||||
}
|
|
||||||
|
|
||||||
static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd)
|
|
||||||
{
|
|
||||||
CPUState *cs = env_cpu(env);
|
|
||||||
ram_addr_t bdloc;
|
|
||||||
int i, n;
|
|
||||||
|
|
||||||
/* We put the bd structure at the top of memory */
|
|
||||||
if (bd->bi_memsize >= 0x01000000UL) {
|
|
||||||
bdloc = 0x01000000UL - sizeof(ppc4xx_bd_info_t);
|
|
||||||
} else {
|
|
||||||
bdloc = bd->bi_memsize - sizeof(ppc4xx_bd_info_t);
|
|
||||||
}
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
|
|
||||||
for (i = 0; i < 6; i++) {
|
|
||||||
stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
|
|
||||||
}
|
|
||||||
stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
|
|
||||||
for (i = 0; i < 4; i++) {
|
|
||||||
stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
|
|
||||||
}
|
|
||||||
for (i = 0; i < 32; i++) {
|
|
||||||
stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
|
|
||||||
}
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_procfreq);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x60, bd->bi_plb_busfreq);
|
|
||||||
stl_be_phys(cs->as, bdloc + 0x64, bd->bi_pci_busfreq);
|
|
||||||
for (i = 0; i < 6; i++) {
|
|
||||||
stb_phys(cs->as, bdloc + 0x68 + i, bd->bi_pci_enetaddr[i]);
|
|
||||||
}
|
|
||||||
n = 0x70; /* includes 2 bytes hole */
|
|
||||||
for (i = 0; i < 6; i++) {
|
|
||||||
stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
|
|
||||||
}
|
|
||||||
stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
|
|
||||||
n += 4;
|
|
||||||
for (i = 0; i < 2; i++) {
|
|
||||||
stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
|
|
||||||
n += 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
return bdloc;
|
|
||||||
}
|
|
||||||
|
|
||||||
static ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size)
|
|
||||||
{
|
|
||||||
ppc4xx_bd_info_t bd;
|
|
||||||
|
|
||||||
memset(&bd, 0, sizeof(bd));
|
|
||||||
|
|
||||||
ppc405_set_default_bootinfo(&bd, ram_size);
|
|
||||||
|
|
||||||
return __ppc405_set_bootinfo(env, &bd);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void boot_from_kernel(MachineState *machine, PowerPCCPU *cpu)
|
|
||||||
{
|
|
||||||
CPUPPCState *env = &cpu->env;
|
|
||||||
hwaddr boot_entry;
|
|
||||||
hwaddr kernel_base;
|
|
||||||
int kernel_size;
|
|
||||||
hwaddr initrd_base;
|
|
||||||
int initrd_size;
|
|
||||||
ram_addr_t bdloc;
|
|
||||||
int len;
|
|
||||||
|
|
||||||
bdloc = ppc405_set_bootinfo(env, machine->ram_size);
|
|
||||||
boot_info.bdloc = bdloc;
|
|
||||||
|
|
||||||
kernel_size = load_elf(machine->kernel_filename, NULL, NULL, NULL,
|
|
||||||
&boot_entry, &kernel_base, NULL, NULL,
|
|
||||||
ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
|
|
||||||
if (kernel_size < 0) {
|
|
||||||
error_report("Could not load kernel '%s' : %s",
|
|
||||||
machine->kernel_filename, load_elf_strerror(kernel_size));
|
|
||||||
exit(1);
|
|
||||||
}
|
|
||||||
boot_info.entry = boot_entry;
|
|
||||||
|
|
||||||
/* load initrd */
|
|
||||||
if (machine->initrd_filename) {
|
|
||||||
initrd_base = INITRD_LOAD_ADDR;
|
|
||||||
initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
|
|
||||||
machine->ram_size - initrd_base);
|
|
||||||
if (initrd_size < 0) {
|
|
||||||
error_report("could not load initial ram disk '%s'",
|
|
||||||
machine->initrd_filename);
|
|
||||||
exit(1);
|
|
||||||
}
|
|
||||||
|
|
||||||
boot_info.initrd_base = initrd_base;
|
|
||||||
boot_info.initrd_size = initrd_size;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (machine->kernel_cmdline) {
|
|
||||||
len = strlen(machine->kernel_cmdline);
|
|
||||||
bdloc -= ((len + 255) & ~255);
|
|
||||||
cpu_physical_memory_write(bdloc, machine->kernel_cmdline, len + 1);
|
|
||||||
boot_info.cmdline_base = bdloc;
|
|
||||||
boot_info.cmdline_size = bdloc + len;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Install our custom reset handler to start from Linux */
|
|
||||||
qemu_register_reset(main_cpu_reset, cpu);
|
|
||||||
env->load_info = &boot_info;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ppc405_init(MachineState *machine)
|
|
||||||
{
|
|
||||||
Ppc405MachineState *ppc405 = PPC405_MACHINE(machine);
|
|
||||||
const char *kernel_filename = machine->kernel_filename;
|
|
||||||
MemoryRegion *sysmem = get_system_memory();
|
|
||||||
|
|
||||||
object_initialize_child(OBJECT(machine), "soc", &ppc405->soc,
|
|
||||||
TYPE_PPC405_SOC);
|
|
||||||
object_property_set_link(OBJECT(&ppc405->soc), "dram",
|
|
||||||
OBJECT(machine->ram), &error_abort);
|
|
||||||
object_property_set_uint(OBJECT(&ppc405->soc), "sys-clk", 33333333,
|
|
||||||
&error_abort);
|
|
||||||
qdev_realize(DEVICE(&ppc405->soc), NULL, &error_fatal);
|
|
||||||
|
|
||||||
/* allocate and load BIOS */
|
|
||||||
if (machine->firmware) {
|
|
||||||
MemoryRegion *bios = g_new(MemoryRegion, 1);
|
|
||||||
g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
|
|
||||||
machine->firmware);
|
|
||||||
long bios_size;
|
|
||||||
|
|
||||||
memory_region_init_rom(bios, NULL, "ef405ep.bios", BIOS_SIZE,
|
|
||||||
&error_fatal);
|
|
||||||
|
|
||||||
if (!filename) {
|
|
||||||
error_report("Could not find firmware '%s'", machine->firmware);
|
|
||||||
exit(1);
|
|
||||||
}
|
|
||||||
|
|
||||||
bios_size = load_image_size(filename,
|
|
||||||
memory_region_get_ram_ptr(bios),
|
|
||||||
BIOS_SIZE);
|
|
||||||
if (bios_size < 0) {
|
|
||||||
error_report("Could not load PowerPC BIOS '%s'", machine->firmware);
|
|
||||||
exit(1);
|
|
||||||
}
|
|
||||||
|
|
||||||
bios_size = (bios_size + 0xfff) & ~0xfff;
|
|
||||||
memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Load kernel and initrd using U-Boot images */
|
|
||||||
if (kernel_filename && machine->firmware) {
|
|
||||||
target_ulong kernel_base, initrd_base;
|
|
||||||
long kernel_size, initrd_size;
|
|
||||||
|
|
||||||
kernel_base = KERNEL_LOAD_ADDR;
|
|
||||||
kernel_size = load_image_targphys(kernel_filename, kernel_base,
|
|
||||||
machine->ram_size - kernel_base);
|
|
||||||
if (kernel_size < 0) {
|
|
||||||
error_report("could not load kernel '%s'", kernel_filename);
|
|
||||||
exit(1);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* load initrd */
|
|
||||||
if (machine->initrd_filename) {
|
|
||||||
initrd_base = INITRD_LOAD_ADDR;
|
|
||||||
initrd_size = load_image_targphys(machine->initrd_filename,
|
|
||||||
initrd_base,
|
|
||||||
machine->ram_size - initrd_base);
|
|
||||||
if (initrd_size < 0) {
|
|
||||||
error_report("could not load initial ram disk '%s'",
|
|
||||||
machine->initrd_filename);
|
|
||||||
exit(1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Load ELF kernel and rootfs.cpio */
|
|
||||||
} else if (kernel_filename && !machine->firmware) {
|
|
||||||
ppc4xx_sdram_ddr_enable(&ppc405->soc.sdram);
|
|
||||||
boot_from_kernel(machine, &ppc405->soc.cpu);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ppc405_machine_class_init(ObjectClass *oc, void *data)
|
|
||||||
{
|
|
||||||
MachineClass *mc = MACHINE_CLASS(oc);
|
|
||||||
|
|
||||||
mc->desc = "PPC405 generic machine";
|
|
||||||
mc->init = ppc405_init;
|
|
||||||
mc->default_ram_size = 128 * MiB;
|
|
||||||
mc->default_ram_id = "ppc405.ram";
|
|
||||||
mc->deprecation_reason = "machine is old and unmaintained";
|
|
||||||
}
|
|
||||||
|
|
||||||
static const TypeInfo ppc405_machine_type = {
|
|
||||||
.name = TYPE_PPC405_MACHINE,
|
|
||||||
.parent = TYPE_MACHINE,
|
|
||||||
.instance_size = sizeof(Ppc405MachineState),
|
|
||||||
.class_init = ppc405_machine_class_init,
|
|
||||||
.abstract = true,
|
|
||||||
};
|
|
||||||
|
|
||||||
/*****************************************************************************/
|
|
||||||
/* PPC405EP reference board (IBM) */
|
|
||||||
/*
|
|
||||||
* Standalone board with:
|
|
||||||
* - PowerPC 405EP CPU
|
|
||||||
* - SDRAM (0x00000000)
|
|
||||||
* - Flash (0xFFF80000)
|
|
||||||
* - SRAM (0xFFF00000)
|
|
||||||
* - NVRAM (0xF0000000)
|
|
||||||
* - FPGA (0xF0300000)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define PPC405EP_NVRAM_BASE 0xF0000000
|
|
||||||
#define PPC405EP_FPGA_BASE 0xF0300000
|
|
||||||
#define PPC405EP_FLASH_BASE 0xFFF80000
|
|
||||||
|
|
||||||
#define TYPE_REF405EP_FPGA "ref405ep-fpga"
|
|
||||||
OBJECT_DECLARE_SIMPLE_TYPE(Ref405epFpgaState, REF405EP_FPGA);
|
|
||||||
struct Ref405epFpgaState {
|
|
||||||
SysBusDevice parent_obj;
|
|
||||||
|
|
||||||
MemoryRegion iomem;
|
|
||||||
|
|
||||||
uint8_t reg0;
|
|
||||||
uint8_t reg1;
|
|
||||||
};
|
|
||||||
|
|
||||||
static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
|
|
||||||
{
|
|
||||||
Ref405epFpgaState *fpga = opaque;
|
|
||||||
uint32_t ret;
|
|
||||||
|
|
||||||
switch (addr) {
|
|
||||||
case 0x0:
|
|
||||||
ret = fpga->reg0;
|
|
||||||
break;
|
|
||||||
case 0x1:
|
|
||||||
ret = fpga->reg1;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
ret = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
|
|
||||||
unsigned size)
|
|
||||||
{
|
|
||||||
Ref405epFpgaState *fpga = opaque;
|
|
||||||
|
|
||||||
switch (addr) {
|
|
||||||
case 0x0:
|
|
||||||
/* Read only */
|
|
||||||
break;
|
|
||||||
case 0x1:
|
|
||||||
fpga->reg1 = value;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static const MemoryRegionOps ref405ep_fpga_ops = {
|
|
||||||
.read = ref405ep_fpga_readb,
|
|
||||||
.write = ref405ep_fpga_writeb,
|
|
||||||
.impl.min_access_size = 1,
|
|
||||||
.impl.max_access_size = 1,
|
|
||||||
.valid.min_access_size = 1,
|
|
||||||
.valid.max_access_size = 4,
|
|
||||||
.endianness = DEVICE_BIG_ENDIAN,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void ref405ep_fpga_reset(DeviceState *dev)
|
|
||||||
{
|
|
||||||
Ref405epFpgaState *fpga = REF405EP_FPGA(dev);
|
|
||||||
|
|
||||||
fpga->reg0 = 0x00;
|
|
||||||
fpga->reg1 = 0x0F;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ref405ep_fpga_realize(DeviceState *dev, Error **errp)
|
|
||||||
{
|
|
||||||
Ref405epFpgaState *s = REF405EP_FPGA(dev);
|
|
||||||
|
|
||||||
memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s,
|
|
||||||
"fpga", 0x00000100);
|
|
||||||
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ref405ep_fpga_class_init(ObjectClass *oc, void *data)
|
|
||||||
{
|
|
||||||
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
||||||
|
|
||||||
dc->realize = ref405ep_fpga_realize;
|
|
||||||
device_class_set_legacy_reset(dc, ref405ep_fpga_reset);
|
|
||||||
/* Reason: only works as part of a ppc405 board */
|
|
||||||
dc->user_creatable = false;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const TypeInfo ref405ep_fpga_type = {
|
|
||||||
.name = TYPE_REF405EP_FPGA,
|
|
||||||
.parent = TYPE_SYS_BUS_DEVICE,
|
|
||||||
.instance_size = sizeof(Ref405epFpgaState),
|
|
||||||
.class_init = ref405ep_fpga_class_init,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void ref405ep_init(MachineState *machine)
|
|
||||||
{
|
|
||||||
DeviceState *dev;
|
|
||||||
SysBusDevice *s;
|
|
||||||
MemoryRegion *sram = g_new(MemoryRegion, 1);
|
|
||||||
|
|
||||||
ppc405_init(machine);
|
|
||||||
|
|
||||||
/* allocate SRAM */
|
|
||||||
memory_region_init_ram(sram, NULL, "ref405ep.sram", PPC405EP_SRAM_SIZE,
|
|
||||||
&error_fatal);
|
|
||||||
memory_region_add_subregion(get_system_memory(), PPC405EP_SRAM_BASE, sram);
|
|
||||||
|
|
||||||
/* Register FPGA */
|
|
||||||
dev = qdev_new(TYPE_REF405EP_FPGA);
|
|
||||||
object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev));
|
|
||||||
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
||||||
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE);
|
|
||||||
|
|
||||||
/* Register NVRAM */
|
|
||||||
dev = qdev_new("sysbus-m48t08");
|
|
||||||
qdev_prop_set_int32(dev, "base-year", 1968);
|
|
||||||
s = SYS_BUS_DEVICE(dev);
|
|
||||||
sysbus_realize_and_unref(s, &error_fatal);
|
|
||||||
sysbus_mmio_map(s, 0, PPC405EP_NVRAM_BASE);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ref405ep_class_init(ObjectClass *oc, void *data)
|
|
||||||
{
|
|
||||||
MachineClass *mc = MACHINE_CLASS(oc);
|
|
||||||
|
|
||||||
mc->desc = "ref405ep";
|
|
||||||
mc->init = ref405ep_init;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const TypeInfo ref405ep_type = {
|
|
||||||
.name = MACHINE_TYPE_NAME("ref405ep"),
|
|
||||||
.parent = TYPE_PPC405_MACHINE,
|
|
||||||
.class_init = ref405ep_class_init,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void ppc405_machine_init(void)
|
|
||||||
{
|
|
||||||
type_register_static(&ppc405_machine_type);
|
|
||||||
type_register_static(&ref405ep_type);
|
|
||||||
type_register_static(&ref405ep_fpga_type);
|
|
||||||
}
|
|
||||||
|
|
||||||
type_init(ppc405_machine_init)
|
|
||||||
1216
hw/ppc/ppc405_uc.c
1216
hw/ppc/ppc405_uc.c
File diff suppressed because it is too large
Load diff
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Add table
Add a link
Reference in a new issue