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aspeed/scu: Add AST2700 support
AST2700 have two SCU controllers which are SCU and SCUIO. Both SCU and SCUIO registers are not compatible previous SOCs , introduces new registers and adds ast2700 scu, sucio class init handler. The pclk divider selection of SCUIO is defined in SCUIO280[20:18] and the pclk divider selection of SCU is defined in SCU280[25:23]. Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function and trace-event for AST2700 SCU and SCUIO. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [clg: Fixed spelling : Unhandeled -> Unhandled ]
This commit is contained in:
Jamin Lin
Cédric Le Goater
parent
bdb3748dba
commit
e7c8106d48
3 changed files with 351 additions and 6 deletions
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@ -134,6 +134,48 @@
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#define AST2600_CLK TO_REG(0x40)
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#define AST2700_SILICON_REV TO_REG(0x00)
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#define AST2700_HW_STRAP1 TO_REG(0x10)
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#define AST2700_HW_STRAP1_CLR TO_REG(0x14)
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#define AST2700_HW_STRAP1_LOCK TO_REG(0x20)
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#define AST2700_HW_STRAP1_SEC1 TO_REG(0x24)
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#define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)
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#define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)
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#define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)
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#define AST2700_SCU_HPLL_PARAM TO_REG(0x300)
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#define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)
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#define AST2700_SCU_DPLL_PARAM TO_REG(0x308)
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#define AST2700_SCU_DPLL_EXT_PARAM TO_REG(0x30c)
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#define AST2700_SCU_MPLL_PARAM TO_REG(0x310)
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#define AST2700_SCU_MPLL_EXT_PARAM TO_REG(0x314)
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#define AST2700_SCU_D1CLK_PARAM TO_REG(0x320)
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#define AST2700_SCU_D2CLK_PARAM TO_REG(0x330)
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#define AST2700_SCU_CRT1CLK_PARAM TO_REG(0x340)
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#define AST2700_SCU_CRT2CLK_PARAM TO_REG(0x350)
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#define AST2700_SCU_MPHYCLK_PARAM TO_REG(0x360)
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#define AST2700_SCU_FREQ_CNTR TO_REG(0x3b0)
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#define AST2700_SCU_CPU_SCRATCH_0 TO_REG(0x780)
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#define AST2700_SCU_CPU_SCRATCH_1 TO_REG(0x784)
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#define AST2700_SCUIO_CLK_STOP_CTL_1 TO_REG(0x240)
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#define AST2700_SCUIO_CLK_STOP_CLR_1 TO_REG(0x244)
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#define AST2700_SCUIO_CLK_STOP_CTL_2 TO_REG(0x260)
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#define AST2700_SCUIO_CLK_STOP_CLR_2 TO_REG(0x264)
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#define AST2700_SCUIO_CLK_SEL_1 TO_REG(0x280)
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#define AST2700_SCUIO_CLK_SEL_2 TO_REG(0x284)
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#define AST2700_SCUIO_HPLL_PARAM TO_REG(0x300)
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#define AST2700_SCUIO_HPLL_EXT_PARAM TO_REG(0x304)
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#define AST2700_SCUIO_APLL_PARAM TO_REG(0x310)
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#define AST2700_SCUIO_APLL_EXT_PARAM TO_REG(0x314)
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#define AST2700_SCUIO_DPLL_PARAM TO_REG(0x320)
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#define AST2700_SCUIO_DPLL_EXT_PARAM TO_REG(0x324)
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#define AST2700_SCUIO_DPLL_PARAM_READ TO_REG(0x328)
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#define AST2700_SCUIO_DPLL_EXT_PARAM_READ TO_REG(0x32c)
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#define AST2700_SCUIO_UARTCLK_GEN TO_REG(0x330)
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#define AST2700_SCUIO_HUARTCLK_GEN TO_REG(0x334)
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#define AST2700_SCUIO_CLK_DUTY_MEAS_RST TO_REG(0x388)
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#define SCU_IO_REGION_SIZE 0x1000
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static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
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@ -244,6 +286,25 @@ static uint32_t aspeed_1030_scu_get_apb_freq(AspeedSCUState *s)
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/ asc->apb_divider;
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}
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static uint32_t aspeed_2700_scu_get_apb_freq(AspeedSCUState *s)
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{
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AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
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uint32_t hpll = asc->calc_hpll(s, s->regs[AST2700_SCU_HPLL_PARAM]);
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return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2700_SCU_CLK_SEL_1]) + 1)
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/ asc->apb_divider;
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}
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static uint32_t aspeed_2700_scuio_get_apb_freq(AspeedSCUState *s)
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{
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AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s);
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uint32_t hpll = asc->calc_hpll(s, s->regs[AST2700_SCUIO_HPLL_PARAM]);
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return hpll /
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(SCUIO_AST2700_CLK_GET_PCLK_DIV(s->regs[AST2700_SCUIO_CLK_SEL_1]) + 1)
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/ asc->apb_divider;
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}
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static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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@ -258,7 +319,8 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
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switch (reg) {
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case RNG_DATA:
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/* On hardware, RNG_DATA works regardless of
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/*
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* On hardware, RNG_DATA works regardless of
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* the state of the enable bit in RNG_CTRL
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*/
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s->regs[RNG_DATA] = aspeed_scu_get_random();
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@ -494,6 +556,9 @@ static uint32_t aspeed_silicon_revs[] = {
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AST2600_A3_SILICON_REV,
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AST1030_A0_SILICON_REV,
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AST1030_A1_SILICON_REV,
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AST2700_A0_SILICON_REV,
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AST2720_A0_SILICON_REV,
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AST2750_A0_SILICON_REV,
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};
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bool is_supported_silicon_rev(uint32_t silicon_rev)
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@ -783,6 +848,243 @@ static const TypeInfo aspeed_2600_scu_info = {
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.class_init = aspeed_2600_scu_class_init,
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};
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static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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int reg = TO_REG(offset);
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if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return 0;
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}
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switch (reg) {
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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trace_aspeed_ast2700_scu_read(offset, size, s->regs[reg]);
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return s->regs[reg];
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}
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static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,
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uint64_t data64, unsigned size)
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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int reg = TO_REG(offset);
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/* Truncate here so bitwise operations below behave as expected */
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uint32_t data = data64;
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if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return;
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}
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trace_aspeed_ast2700_scu_write(offset, size, data);
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switch (reg) {
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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s->regs[reg] = data;
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}
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static const MemoryRegionOps aspeed_ast2700_scu_ops = {
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.read = aspeed_ast2700_scu_read,
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.write = aspeed_ast2700_scu_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.valid.unaligned = false,
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};
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static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
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[AST2700_SILICON_REV] = AST2700_A0_SILICON_REV,
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[AST2700_HW_STRAP1] = 0x00000800,
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[AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,
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[AST2700_HW_STRAP1_LOCK] = 0x00000FFF,
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[AST2700_HW_STRAP1_SEC1] = 0x000000FF,
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[AST2700_HW_STRAP1_SEC2] = 0x00000000,
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[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
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[AST2700_SCU_HPLL_PARAM] = 0x0000009f,
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[AST2700_SCU_HPLL_EXT_PARAM] = 0x8000004f,
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[AST2700_SCU_DPLL_PARAM] = 0x0080009f,
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[AST2700_SCU_DPLL_EXT_PARAM] = 0x8000004f,
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[AST2700_SCU_MPLL_PARAM] = 0x00000040,
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[AST2700_SCU_MPLL_EXT_PARAM] = 0x80000000,
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[AST2700_SCU_D1CLK_PARAM] = 0x00050002,
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[AST2700_SCU_D2CLK_PARAM] = 0x00050002,
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[AST2700_SCU_CRT1CLK_PARAM] = 0x00050002,
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[AST2700_SCU_CRT2CLK_PARAM] = 0x00050002,
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[AST2700_SCU_MPHYCLK_PARAM] = 0x0000004c,
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[AST2700_SCU_FREQ_CNTR] = 0x000375eb,
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[AST2700_SCU_CPU_SCRATCH_0] = 0x00000000,
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[AST2700_SCU_CPU_SCRATCH_1] = 0x00000004,
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};
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static void aspeed_ast2700_scu_reset(DeviceState *dev)
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{
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AspeedSCUState *s = ASPEED_SCU(dev);
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AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
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memcpy(s->regs, asc->resets, asc->nr_regs * 4);
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}
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static void aspeed_2700_scu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
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dc->desc = "ASPEED 2700 System Control Unit";
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dc->reset = aspeed_ast2700_scu_reset;
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asc->resets = ast2700_a0_resets;
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asc->calc_hpll = aspeed_2600_scu_calc_hpll;
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asc->get_apb = aspeed_2700_scu_get_apb_freq;
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asc->apb_divider = 4;
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asc->nr_regs = ASPEED_AST2700_SCU_NR_REGS;
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asc->clkin_25Mhz = true;
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asc->ops = &aspeed_ast2700_scu_ops;
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}
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static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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int reg = TO_REG(offset);
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if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return 0;
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}
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switch (reg) {
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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trace_aspeed_ast2700_scuio_read(offset, size, s->regs[reg]);
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return s->regs[reg];
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}
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static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset,
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uint64_t data64, unsigned size)
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{
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AspeedSCUState *s = ASPEED_SCU(opaque);
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int reg = TO_REG(offset);
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/* Truncate here so bitwise operations below behave as expected */
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uint32_t data = data64;
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bool updated = false;
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if (reg >= ASPEED_AST2700_SCU_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return;
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}
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trace_aspeed_ast2700_scuio_write(offset, size, data);
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switch (reg) {
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case AST2700_SCUIO_CLK_STOP_CTL_1:
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case AST2700_SCUIO_CLK_STOP_CTL_2:
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s->regs[reg] |= data;
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updated = true;
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break;
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case AST2700_SCUIO_CLK_STOP_CLR_1:
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case AST2700_SCUIO_CLK_STOP_CLR_2:
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s->regs[reg - 1] ^= data;
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updated = true;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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break;
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}
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if (!updated) {
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s->regs[reg] = data;
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}
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}
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static const MemoryRegionOps aspeed_ast2700_scuio_ops = {
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.read = aspeed_ast2700_scuio_read,
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.write = aspeed_ast2700_scuio_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.valid.unaligned = false,
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};
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static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {
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[AST2700_SILICON_REV] = 0x06000003,
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[AST2700_HW_STRAP1] = 0x00000504,
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[AST2700_HW_STRAP1_CLR] = 0xFFF0FFF0,
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[AST2700_HW_STRAP1_LOCK] = 0x00000FFF,
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[AST2700_HW_STRAP1_SEC1] = 0x000000FF,
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[AST2700_HW_STRAP1_SEC2] = 0x00000000,
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[AST2700_HW_STRAP1_SEC3] = 0x1000408F,
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[AST2700_SCUIO_CLK_STOP_CTL_1] = 0xffff8400,
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[AST2700_SCUIO_CLK_STOP_CTL_2] = 0x00005f30,
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[AST2700_SCUIO_CLK_SEL_1] = 0x86900000,
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[AST2700_SCUIO_CLK_SEL_2] = 0x00400000,
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[AST2700_SCUIO_HPLL_PARAM] = 0x10000027,
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[AST2700_SCUIO_HPLL_EXT_PARAM] = 0x80000014,
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[AST2700_SCUIO_APLL_PARAM] = 0x1000001f,
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[AST2700_SCUIO_APLL_EXT_PARAM] = 0x8000000f,
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[AST2700_SCUIO_DPLL_PARAM] = 0x106e42ce,
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[AST2700_SCUIO_DPLL_EXT_PARAM] = 0x80000167,
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[AST2700_SCUIO_DPLL_PARAM_READ] = 0x106e42ce,
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[AST2700_SCUIO_DPLL_EXT_PARAM_READ] = 0x80000167,
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[AST2700_SCUIO_UARTCLK_GEN] = 0x00014506,
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[AST2700_SCUIO_HUARTCLK_GEN] = 0x000145c0,
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[AST2700_SCUIO_CLK_DUTY_MEAS_RST] = 0x0c9100d2,
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};
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static void aspeed_2700_scuio_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
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dc->desc = "ASPEED 2700 System Control Unit I/O";
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dc->reset = aspeed_ast2700_scu_reset;
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asc->resets = ast2700_a0_resets_io;
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asc->calc_hpll = aspeed_2600_scu_calc_hpll;
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asc->get_apb = aspeed_2700_scuio_get_apb_freq;
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asc->apb_divider = 2;
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asc->nr_regs = ASPEED_AST2700_SCU_NR_REGS;
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asc->clkin_25Mhz = true;
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asc->ops = &aspeed_ast2700_scuio_ops;
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}
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static const TypeInfo aspeed_2700_scu_info = {
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.name = TYPE_ASPEED_2700_SCU,
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.parent = TYPE_ASPEED_SCU,
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.instance_size = sizeof(AspeedSCUState),
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.class_init = aspeed_2700_scu_class_init,
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};
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static const TypeInfo aspeed_2700_scuio_info = {
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.name = TYPE_ASPEED_2700_SCUIO,
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.parent = TYPE_ASPEED_SCU,
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.instance_size = sizeof(AspeedSCUState),
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.class_init = aspeed_2700_scuio_class_init,
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};
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static const uint32_t ast1030_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
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[AST2600_SYS_RST_CTRL] = 0xFFC3FED8,
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[AST2600_SYS_RST_CTRL2] = 0x09FFFFFC,
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@ -841,6 +1143,8 @@ static void aspeed_scu_register_types(void)
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type_register_static(&aspeed_2500_scu_info);
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type_register_static(&aspeed_2600_scu_info);
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type_register_static(&aspeed_1030_scu_info);
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type_register_static(&aspeed_2700_scu_info);
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type_register_static(&aspeed_2700_scuio_info);
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}
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type_init(aspeed_scu_register_types);
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