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hw/intc: RX62N interrupt controller (ICUa)

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This implementation supported only ICUa.
Hardware manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200224141923.82118-15-ysato@users.sourceforge.jp>
[PMD: Fill VMStateField for migration, cover files in MAINTAINERS]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Yoshinori Sato 2019-01-21 22:15:57 +09:00 • committed by Philippe Mathieu-Daudé
parent f4d2382a9b
commit e78597cc45
5 changed files with 483 additions and 0 deletions
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76
include/hw/intc/rx_icu.h Normal file
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/*
* RX Interrupt Control Unit
*
* Copyright (c) 2019 Yoshinori Sato
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef HW_INTC_RX_ICU_H
#define HW_INTC_RX_ICU_H
#include "hw/sysbus.h"
enum TRG_MODE {
TRG_LEVEL = 0,
TRG_NEDGE = 1, /* Falling */
TRG_PEDGE = 2, /* Raising */
TRG_BEDGE = 3, /* Both */
};
struct IRQSource {
enum TRG_MODE sense;
int level;
};
enum {
/* Software interrupt request */
SWI = 27,
NR_IRQS = 256
};
struct RXICUState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion memory;
struct IRQSource src[NR_IRQS];
uint32_t nr_irqs;
uint8_t *map;
uint32_t nr_sense;
uint8_t *init_sense;
uint8_t ir[NR_IRQS];
uint8_t dtcer[NR_IRQS];
uint8_t ier[NR_IRQS / 8];
uint8_t ipr[142];
uint8_t dmasr[4];
uint16_t fir;
uint8_t nmisr;
uint8_t nmier;
uint8_t nmiclr;
uint8_t nmicr;
int16_t req_irq;
qemu_irq _irq;
qemu_irq _fir;
qemu_irq _swi;
};
typedef struct RXICUState RXICUState;
#define TYPE_RX_ICU "rx-icu"
#define RX_ICU(obj) OBJECT_CHECK(RXICUState, (obj), TYPE_RX_ICU)
#endif /* RX_ICU_H */