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target/loongarch: Support LoongArch32 TLB entry

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The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-2-philmd@linaro.org>
This commit is contained in:
Jiajie Chen 2023-08-22 09:13:47 +02:00 • committed by Song Gao
parent ebda3036e1
commit e70bb6fb9a
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GPG key ID: 40A2FFF239263EDF
2 changed files with 17 additions and 9 deletions
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9
target/loongarch/cpu-csr.h
View file

@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
FIELD(TLBENTRY, PLV, 2, 2) FIELD(TLBENTRY, PLV, 2, 2)
FIELD(TLBENTRY, MAT, 4, 2) FIELD(TLBENTRY, MAT, 4, 2)
FIELD(TLBENTRY, G, 6, 1) FIELD(TLBENTRY, G, 6, 1)
FIELD(TLBENTRY, PPN, 12, 36) FIELD(TLBENTRY_32, PPN, 8, 24)
FIELD(TLBENTRY, NR, 61, 1) FIELD(TLBENTRY_64, PPN, 12, 36)
FIELD(TLBENTRY, NX, 62, 1) FIELD(TLBENTRY_64, NR, 61, 1)
FIELD(TLBENTRY, RPLV, 63, 1) FIELD(TLBENTRY_64, NX, 62, 1)
FIELD(TLBENTRY_64, RPLV, 63, 1)
#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */ #define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
FIELD(CSR_ASID, ASID, 0, 10) FIELD(CSR_ASID, ASID, 0, 10)

17
target/loongarch/tlb_helper.c
View file

@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V); tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D); tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV); tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN); if (is_la64(env)) {
tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX); tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR); tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV); tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
} else {
tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
tlb_nx = 0;
tlb_nr = 0;
tlb_rplv = 0;
}
/* Check access rights */ /* Check access rights */
if (!tlb_v) { if (!tlb_v) {
@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
* tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15] * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
* need adjust. * need adjust.
*/ */
*physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) | *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
(address & MAKE_64BIT_MASK(0, tlb_ps)); (address & MAKE_64BIT_MASK(0, tlb_ps));
*prot = PAGE_READ; *prot = PAGE_READ;
if (tlb_d) { if (tlb_d) {