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hw/arm/aspeed_ast27x0: Fix RAM size detection failure on BE hosts

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On big-endian hosts, the aspeed_ram_capacity_write() function previously passed
the address of a 64-bit "data" variable directly to address_space_write(),
assuming host and guest endianness matched.

However, the data is expected to be written in little-endian format to DRAM.
On big-endian hosts, this led to incorrect data being written into DRAM,
which caused the guest firmware to misdetect the DRAM size.

As a result, U-Boot fails to boot and hangs.

- Replaces the "address_space_write()" call with "address_space_stl_le()",
  which performs an explicit 32-bit little-endian write.
- Updating the MemoryRegionOps to restrict access to exactly 4 bytes
  using .valid.{min,max}_access_size = 4 and .impl.min_access_size = 4.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: 7436db1 ("aspeed/soc: fix incorrect dram size for AST2700")
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250522023305.2486536-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-05-22 10:33:04 +08:00 • committed by Cédric Le Goater
parent 567accba67
commit e6941ac106
1 changed files with 6 additions and 4 deletions
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10
hw/arm/aspeed_ast27x0.c
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@ -346,8 +346,9 @@ static void aspeed_ram_capacity_write(void *opaque, hwaddr addr, uint64_t data,
* If writes the data to the address which is beyond the ram size, * If writes the data to the address which is beyond the ram size,
* it would write the data to the "address % ram_size". * it would write the data to the "address % ram_size".
*/ */
result = address_space_write(&s->dram_as, addr % ram_size, address_space_stl_le(&s->dram_as, addr % ram_size, data,
MEMTXATTRS_UNSPECIFIED, &data, 4); MEMTXATTRS_UNSPECIFIED, &result);
if (result != MEMTX_OK) { if (result != MEMTX_OK) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"%s: DRAM write failed, addr:0x%" HWADDR_PRIx "%s: DRAM write failed, addr:0x%" HWADDR_PRIx
@ -360,9 +361,10 @@ static const MemoryRegionOps aspeed_ram_capacity_ops = {
.read = aspeed_ram_capacity_read, .read = aspeed_ram_capacity_read,
.write = aspeed_ram_capacity_write, .write = aspeed_ram_capacity_write,
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
.impl.min_access_size = 4,
.valid = { .valid = {
.min_access_size = 1, .min_access_size = 4,
.max_access_size = 8, .max_access_size = 4,
}, },
}; };