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tcg: Convert nand to TCGOutOpBinary

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-06 16:18:19 -08:00
parent 5c0968a7e1
commit e5a3162cb6
24 changed files with 72 additions and 45 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tcg/aarch64/tcg-target-has.h
View file

@ -19,7 +19,6 @@
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1
@ -42,7 +41,6 @@
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1

4
tcg/aarch64/tcg-target.c.inc
View file

@ -2168,6 +2168,10 @@ static const TCGOutOpBinary outop_eqv = {
.out_rrr = tgen_eqv,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

1
tcg/arm/tcg-target-has.h
View file

@ -28,7 +28,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions

4
tcg/arm/tcg-target.c.inc
View file

@ -1885,6 +1885,10 @@ static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

2
tcg/i386/tcg-target-has.h
View file

@ -31,7 +31,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1
@ -54,7 +53,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1

4
tcg/i386/tcg-target.c.inc
View file

@ -2637,6 +2637,10 @@ static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

2
tcg/loongarch64/tcg-target-has.h
View file

@ -25,7 +25,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1
@ -44,7 +43,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1

4
tcg/loongarch64/tcg-target.c.inc
View file

@ -1332,6 +1332,10 @@ static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

2
tcg/mips/tcg-target-has.h
View file

@ -43,7 +43,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muluh_i32 1
@ -60,7 +59,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)

4
tcg/mips/tcg-target.c.inc
View file

@ -1716,6 +1716,10 @@ static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

2
tcg/ppc/tcg-target-has.h
View file

@ -23,7 +23,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 have_isa_3_00
@ -47,7 +46,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 have_isa_3_00

17
tcg/ppc/tcg-target.c.inc
View file

@ -2965,6 +2965,17 @@ static const TCGOutOpBinary outop_eqv = {
.out_rrr = tgen_eqv,
};
static void tgen_nand(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out32(s, NAND | SAB(a1, a0, a2));
}
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_nand,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -3097,10 +3108,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_nand_i32:
case INDEX_op_nand_i64:
tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
break;
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
@ -4172,11 +4179,9 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_divu_i32:
case INDEX_op_rem_i32:
case INDEX_op_remu_i32:
case INDEX_op_nand_i32:
case INDEX_op_nor_i32:
case INDEX_op_muluh_i32:
case INDEX_op_mulsh_i32:
case INDEX_op_nand_i64:
case INDEX_op_nor_i64:
case INDEX_op_div_i64:
case INDEX_op_divu_i64:

2
tcg/riscv/tcg-target-has.h
View file

@ -25,7 +25,6 @@
#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB)
@ -43,7 +42,6 @@
#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB)

4
tcg/riscv/tcg-target.c.inc
View file

@ -2017,6 +2017,10 @@ static const TCGOutOpBinary outop_eqv = {
.out_rrr = tgen_eqv,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

2
tcg/s390x/tcg-target-has.h
View file

@ -34,7 +34,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nand_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nor_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0
@ -56,7 +55,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nand_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nor_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 0

24
tcg/s390x/tcg-target.c.inc
View file

@ -2258,6 +2258,22 @@ static const TCGOutOpBinary outop_eqv = {
.out_rrr = tgen_eqv,
};
static void tgen_nand(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RRFa, NNRK, a0, a1, a2);
} else {
tcg_out_insn(s, RRFa, NNGRK, a0, a1, a2);
}
}
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_misc3_rrr,
.out_rrr = tgen_nand,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -2392,9 +2408,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_nand_i32:
tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]);
break;
case INDEX_op_nor_i32:
tcg_out_insn(s, RRFa, NORK, args[0], args[1], args[2]);
break;
@ -2602,9 +2615,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_nand_i64:
tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]);
break;
case INDEX_op_nor_i64:
tcg_out_insn(s, RRFa, NOGRK, args[0], args[1], args[2]);
break;
@ -3288,8 +3298,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i64:
return C_O1_I2(r, r, ri);
case INDEX_op_nand_i32:
case INDEX_op_nand_i64:
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
return C_O1_I2(r, r, r);

2
tcg/sparc64/tcg-target-has.h
View file

@ -20,7 +20,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_bswap32_i32 0
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0
@ -43,7 +42,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0

4
tcg/sparc64/tcg-target.c.inc
View file

@ -1337,6 +1337,10 @@ static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

1
tcg/tcg-has.h
View file

@ -20,7 +20,6 @@
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 0
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0

4
tcg/tcg-op.c
View file

@ -690,7 +690,7 @@ void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_HAS_nand_i32) {
if (tcg_op_supported(INDEX_op_nand_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_nand_i32, ret, arg1, arg2);
} else {
tcg_gen_and_i32(ret, arg1, arg2);
@ -2292,7 +2292,7 @@ void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_nand_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
tcg_gen_nand_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
} else if (TCG_TARGET_HAS_nand_i64) {
} else if (tcg_op_supported(INDEX_op_nand_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_nand_i64, ret, arg1, arg2);
} else {
tcg_gen_and_i64(ret, arg1, arg2);

8
tcg/tcg.c
View file

@ -1008,6 +1008,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_nand_i32, TCGOutOpBinary, outop_nand),
OUTOP(INDEX_op_nand_i64, TCGOutOpBinary, outop_nand),
OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or),
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_xor, TCGOutOpBinary, outop_xor),
@ -2274,8 +2276,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_bswap32_i32;
case INDEX_op_not_i32:
return TCG_TARGET_HAS_not_i32;
case INDEX_op_nand_i32:
return TCG_TARGET_HAS_nand_i32;
case INDEX_op_nor_i32:
return TCG_TARGET_HAS_nor_i32;
case INDEX_op_clz_i32:
@ -2343,8 +2343,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_bswap64_i64;
case INDEX_op_not_i64:
return TCG_TARGET_HAS_not_i64;
case INDEX_op_nand_i64:
return TCG_TARGET_HAS_nand_i64;
case INDEX_op_nor_i64:
return TCG_TARGET_HAS_nor_i64;
case INDEX_op_clz_i64:
@ -5436,6 +5434,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_and:
case INDEX_op_andc:
case INDEX_op_eqv:
case INDEX_op_nand_i32:
case INDEX_op_nand_i64:
case INDEX_op_or:
case INDEX_op_orc:
case INDEX_op_xor:

2
tcg/tci.c
View file

@ -559,12 +559,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ~(regs[r1] ^ regs[r2]);
break;
#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64
CASE_32_64(nand)
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ~(regs[r1] & regs[r2]);
break;
#endif
#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64
CASE_32_64(nor)
tci_args_rrr(insn, &r0, &r1, &r2);

2
tcg/tci/tcg-target-has.h
View file

@ -12,7 +12,6 @@
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_nand_i32 1
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_clz_i32 1
#define TCG_TARGET_HAS_ctz_i32 1
@ -33,7 +32,6 @@
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_clz_i64 1
#define TCG_TARGET_HAS_ctz_i64 1

14
tcg/tci/tcg-target.c.inc
View file

@ -95,8 +95,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
case INDEX_op_nand_i32:
case INDEX_op_nand_i64:
case INDEX_op_nor_i32:
case INDEX_op_nor_i64:
case INDEX_op_shl_i32:
@ -671,6 +669,17 @@ static const TCGOutOpBinary outop_eqv = {
.out_rrr = tgen_eqv,
};
static void tgen_nand(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_op_rrr(s, glue(INDEX_op_nand_i,TCG_TARGET_REG_BITS), a0, a1, a2);
}
static const TCGOutOpBinary outop_nand = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_nand,
};
static void tgen_or(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -748,7 +757,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
CASE_32_64(sub)
CASE_32_64(mul)
CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */
CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */
CASE_32_64(shl)
CASE_32_64(shr)