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target/riscv: line up all of the registers in the info register dump

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Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.

Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Travis Geiselbrecht 2021-10-08 22:50:19 -07:00 • committed by Alistair Francis
parent c672f19f32
commit e573a7f325
1 changed files with 5 additions and 5 deletions
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6
target/riscv/cpu.c
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@ -258,7 +258,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} }
if (riscv_has_ext(env, RVH)) { if (riscv_has_ext(env, RVH)) {
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus",
(target_ulong)env->vsstatus); (target_ulong)env->vsstatus);
} }
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
@ -298,7 +298,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#endif #endif
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
qemu_fprintf(f, " %s " TARGET_FMT_lx, qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
riscv_int_regnames[i], env->gpr[i]); riscv_int_regnames[i], env->gpr[i]);
if ((i & 3) == 3) { if ((i & 3) == 3) {
qemu_fprintf(f, "\n"); qemu_fprintf(f, "\n");
@ -306,7 +306,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
} }
if (flags & CPU_DUMP_FPU) { if (flags & CPU_DUMP_FPU) {
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
qemu_fprintf(f, " %s %016" PRIx64, qemu_fprintf(f, " %-8s %016" PRIx64,
riscv_fpr_regnames[i], env->fpr[i]); riscv_fpr_regnames[i], env->fpr[i]);
if ((i & 3) == 3) { if ((i & 3) == 3) {
qemu_fprintf(f, "\n"); qemu_fprintf(f, "\n");