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hw: Use device_class_set_legacy_reset() instead of opencoding

Browse source 
Use device_class_set_legacy_reset() instead of opencoding an
assignment to DeviceClass::reset. This change was produced
with:
 spatch --macro-file scripts/cocci-macro-file.h \
    --sp-file scripts/coccinelle/device-reset.cocci \
    --keep-comments --smpl-spacing --in-place --dir hw

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2024-09-13 15:31:44 +01:00
parent 134e0944f4
commit e3d0814368
410 changed files with 448 additions and 448 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/pci-bridge/cxl_downstream.c
View file

@ -236,7 +236,7 @@ static void cxl_dsp_class_init(ObjectClass *oc, void *data)
k->revision = 0;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->desc = "CXL Switch Downstream Port";
dc->reset = cxl_dsp_reset;
device_class_set_legacy_reset(dc, cxl_dsp_reset);
}
static const TypeInfo cxl_dsp_info = {

2
hw/pci-bridge/cxl_upstream.c
View file

@ -380,7 +380,7 @@ static void cxl_upstream_class_init(ObjectClass *oc, void *data)
k->revision = 0;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->desc = "CXL Switch Upstream Port";
dc->reset = cxl_usp_reset;
device_class_set_legacy_reset(dc, cxl_usp_reset);
device_class_set_props(dc, cxl_upstream_props);
}

2
hw/pci-bridge/i82801b11.c
View file

@ -98,7 +98,7 @@ static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
k->realize = i82801b11_bridge_realize;
k->config_write = pci_bridge_write_config;
dc->vmsd = &i82801b11_bridge_dev_vmstate;
dc->reset = pci_bridge_reset;
device_class_set_legacy_reset(dc, pci_bridge_reset);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
}

2
hw/pci-bridge/pci_bridge_dev.c
View file

@ -254,7 +254,7 @@ static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE;
k->class_id = PCI_CLASS_BRIDGE_PCI;
dc->desc = "Standard PCI Bridge";
dc->reset = qdev_pci_bridge_dev_reset;
device_class_set_legacy_reset(dc, qdev_pci_bridge_dev_reset);
device_class_set_props(dc, pci_bridge_dev_properties);
dc->vmsd = &pci_bridge_dev_vmstate;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);

2
hw/pci-bridge/pci_expander_bridge.c
View file

@ -515,7 +515,7 @@ static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data)
/* Host bridges aren't hotpluggable. FIXME: spec reference */
dc->hotpluggable = false;
dc->reset = pxb_cxl_dev_reset;
device_class_set_legacy_reset(dc, pxb_cxl_dev_reset);
}
static const TypeInfo pxb_cxl_dev_info = {

2
hw/pci-bridge/pcie_pci_bridge.c
View file

@ -152,7 +152,7 @@ static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data)
k->config_write = pcie_pci_bridge_write_config;
dc->vmsd = &pcie_pci_bridge_dev_vmstate;
device_class_set_props(dc, pcie_pci_bridge_dev_properties);
dc->reset = &pcie_pci_bridge_reset;
device_class_set_legacy_reset(dc, pcie_pci_bridge_reset);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
hc->plug = pci_bridge_dev_plug_cb;
hc->unplug = pci_bridge_dev_unplug_cb;

2
hw/pci-bridge/simba.c
View file

@ -78,7 +78,7 @@ static void simba_pci_bridge_class_init(ObjectClass *klass, void *data)
k->revision = 0x11;
k->config_write = pci_bridge_write_config;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->reset = pci_bridge_reset;
device_class_set_legacy_reset(dc, pci_bridge_reset);
dc->vmsd = &vmstate_pci_device;
}

2
hw/pci-bridge/xio3130_downstream.c
View file

@ -167,7 +167,7 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
k->revision = XIO3130_REVISION;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
dc->reset = xio3130_downstream_reset;
device_class_set_legacy_reset(dc, xio3130_downstream_reset);
dc->vmsd = &vmstate_xio3130_downstream;
device_class_set_props(dc, xio3130_downstream_props);
}

2
hw/pci-bridge/xio3130_upstream.c
View file

@ -136,7 +136,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
k->revision = XIO3130_REVISION;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
dc->reset = xio3130_upstream_reset;
device_class_set_legacy_reset(dc, xio3130_upstream_reset);
dc->vmsd = &vmstate_xio3130_upstream;
}