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* qdev: second part of Property cleanups

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* rust: second part of QOM rework
 * rust: callbacks wrapper
 * rust: pl011 bugfixes
 * kvm: cleanup errors in kvm_convert_memory()
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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* qdev: second part of Property cleanups
* rust: second part of QOM rework
* rust: callbacks wrapper
* rust: pl011 bugfixes
* kvm: cleanup errors in kvm_convert_memory()

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 # gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
 # gpg:                issuer "pbonzini@redhat.com"
 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
 # gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (42 commits)
  rust: pl011: simplify handling of the FIFO enabled bit in LCR
  rust: pl011: fix migration stream
  rust: pl011: extend registers to 32 bits
  rust: pl011: fix break errors and definition of Data struct
  rust: pl011: always use reset() method on registers
  rust: pl011: match break logic of C version
  rust: pl011: fix declaration of LineControl bits
  target/i386: Reset TSCs of parked vCPUs too on VM reset
  kvm: consistently return 0/-errno from kvm_convert_memory
  rust: qemu-api: add a module to wrap functions and zero-sized closures
  rust: qom: add initial subset of methods on Object
  rust: qom: add casting functionality
  rust: tests: allow writing more than one test
  bql: add a "mock" BQL for Rust unit tests
  rust: re-export C types from qemu-api submodules
  rust: rename qemu-api modules to follow C code a bit more
  rust: qom: add possibility of overriding unparent
  rust: qom: put class_init together from multiple ClassInitImpl<>
  Constify all opaque Property pointers
  hw/core/qdev-properties: Constify Property argument to PropertyInfo.print
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2024-12-21 08:06:50 -05:00
commit e3a207722b
603 changed files with 1422 additions and 1269 deletions
Download patch file Download diff file Expand all files Collapse all files

1
target/arm/cpu.c
View file

@ -2652,7 +2652,6 @@ static const Property arm_cpu_properties[] = {
DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
/* True to default to the backward-compat old CNTFRQ rather than 1Ghz */
DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false),
DEFINE_PROP_END_OF_LIST()
};
static const gchar *arm_gdb_arch_name(CPUState *cs)

1
target/avr/cpu.c
View file

@ -151,7 +151,6 @@ static void avr_cpu_initfn(Object *obj)
static const Property avr_cpu_properties[] = {
DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0),
DEFINE_PROP_END_OF_LIST()
};
static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)

1
target/hexagon/cpu.c
View file

@ -53,7 +53,6 @@ static const Property hexagon_cpu_properties[] = {
DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0,
qdev_prop_uint32, target_ulong),
DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true),
DEFINE_PROP_END_OF_LIST()
};
const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {

2
target/i386/cpu.c
View file

@ -5387,7 +5387,6 @@ static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
static const Property max_x86_cpu_properties[] = {
DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
DEFINE_PROP_END_OF_LIST()
};
static void max_x86_cpu_realize(DeviceState *dev, Error **errp)
@ -8548,7 +8547,6 @@ static const Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
true),
DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true),
DEFINE_PROP_END_OF_LIST()
};
#ifndef CONFIG_USER_ONLY

15
target/i386/kvm/kvm.c
View file

@ -2415,6 +2415,21 @@ void kvm_arch_after_reset_vcpu(X86CPU *cpu)
}
}
void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd)
{
g_autofree struct kvm_msrs *msrs = NULL;
msrs = g_malloc0(sizeof(*msrs) + sizeof(msrs->entries[0]));
msrs->entries[0].index = MSR_IA32_TSC;
msrs->entries[0].data = 1; /* match the value in x86_cpu_reset() */
msrs->nmsrs++;
if (ioctl(kvm_fd, KVM_SET_MSRS, msrs) != 1) {
warn_report("parked vCPU %lu TSC reset failed: %d",
vcpu_id, errno);
}
}
void kvm_arch_do_init_vcpu(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;

1
target/microblaze/cpu.c
View file

@ -403,7 +403,6 @@ static const Property mb_properties[] = {
/*
* End of properties reserved by Xilinx DTS conversion tool.
*/
DEFINE_PROP_END_OF_LIST(),
};
static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)

1
target/mips/cpu.c
View file

@ -541,7 +541,6 @@ static const struct SysemuCPUOps mips_sysemu_ops = {
static const Property mips_cpu_properties[] = {
DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN),
DEFINE_PROP_END_OF_LIST(),
};
#ifdef CONFIG_TCG

6
target/ppc/cpu_init.c
View file

@ -7414,11 +7414,6 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
#endif
}
static Property ppc_cpu_properties[] = {
/* add default property here */
DEFINE_PROP_END_OF_LIST(),
};
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
@ -7468,7 +7463,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
&pcc->parent_unrealize);
pcc->pvr_match = ppc_pvr_match_default;
device_class_set_props(dc, ppc_cpu_properties);
resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
&pcc->parent_phases);

13
target/riscv/cpu.c
View file

@ -213,7 +213,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
DEFINE_PROP_END_OF_LIST(),
{ },
};
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
@ -1575,7 +1575,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false),
MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false),
DEFINE_PROP_END_OF_LIST(),
{ },
};
const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
@ -1592,12 +1592,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
DEFINE_PROP_END_OF_LIST(),
{ },
};
/* These are experimental so mark with 'x-' */
const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
DEFINE_PROP_END_OF_LIST(),
{ },
};
/*
@ -1610,7 +1610,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
DEFINE_PROP_END_OF_LIST(),
{ },
};
/* Deprecated entries marked for future removal */
@ -1627,7 +1627,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
DEFINE_PROP_END_OF_LIST(),
{ },
};
static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname,
@ -2699,7 +2699,6 @@ static const Property riscv_cpu_properties[] = {
* it with -x and default to 'false'.
*/
DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
DEFINE_PROP_END_OF_LIST(),
};
#if defined(TARGET_RISCV64)

7
target/s390x/cpu.c
View file

@ -309,8 +309,8 @@ static const gchar *s390_gdb_arch_name(CPUState *cs)
return "s390:64-bit";
}
#ifndef CONFIG_USER_ONLY
static const Property s390x_cpu_properties[] = {
#if !defined(CONFIG_USER_ONLY)
DEFINE_PROP_UINT32("core-id", S390CPU, env.core_id, 0),
DEFINE_PROP_INT32("socket-id", S390CPU, env.socket_id, -1),
DEFINE_PROP_INT32("book-id", S390CPU, env.book_id, -1),
@ -318,9 +318,8 @@ static const Property s390x_cpu_properties[] = {
DEFINE_PROP_BOOL("dedicated", S390CPU, env.dedicated, false),
DEFINE_PROP_CPUS390ENTITLEMENT("entitlement", S390CPU, env.entitlement,
S390_CPU_ENTITLEMENT_AUTO),
#endif
DEFINE_PROP_END_OF_LIST()
};
#endif
#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
@ -388,7 +387,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, s390_cpu_realizefn,
&scc->parent_realize);
device_class_set_props(dc, s390x_cpu_properties);
dc->user_creatable = true;
resettable_class_set_parent_phases(rc, NULL, s390_cpu_reset_hold, NULL,
@ -404,6 +402,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
device_class_set_props(dc, s390x_cpu_properties);
s390_cpu_class_init_sysemu(cc);
#endif
cc->disas_set_info = s390_cpu_disas_set_info;

1
target/sparc/cpu.c
View file

@ -917,7 +917,6 @@ static const Property sparc_cpu_properties[] = {
DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows,
qdev_prop_nwindows, uint32_t),
DEFINE_PROP_END_OF_LIST()
};
#ifndef CONFIG_USER_ONLY