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Third RISC-V PR for 6.1 release
- Fix MISA in the DisasContext - Fix GDB CSR XML generation - QOMify the SiFive UART - Add support for the OpenTitan timer -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmDUc9oACgkQIeENKd+X cFQnJQf/YJ1DcCc5HKnJD7dKOO7auWGrjcBydVLZpCKT/sBYO2m4+LcUoCkndJst z2awR2sL6zgTqkpKTFJzENBKcXf0NOAvGvuvAznPQosvW26NhY20EsWHgRxn79DF 2CvFChD4J/aBZa/JwP7232CebsD2IqKn89gP5u6ldFNH36EGpzBRjFOroXLu98x3 arhr7AoyhTTpxcWkWuLW9YVwqZQ8xKKCVTMuqMC8SRI48FUB5+ndy3pTQqIjdoCg U0wfJIrmPBakw3ik0nbNd47Lu/yxCQMU/O4M/flSbbC1GpomiUotlap9O3LlvNYo 7VeF8eS3/7Okn2/5jEwuFES+MmtUSQ== =zVjG -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210624-2' into staging Third RISC-V PR for 6.1 release - Fix MISA in the DisasContext - Fix GDB CSR XML generation - QOMify the SiFive UART - Add support for the OpenTitan timer # gpg: Signature made Thu 24 Jun 2021 13:00:26 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210624-2: hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer hw/timer: Initial commit of Ibex Timer hw/char/ibex_uart: Make the register layout private hw/char: QOMify sifive_uart hw/char: Consistent function names for sifive_uart target/riscv: gdbstub: Fix dynamic CSR XML generation target/riscv: Use target_ulong for the DisasContext misa Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
e3955ae93f
12 changed files with 543 additions and 81 deletions
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@ -31,43 +31,6 @@
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#include "qemu/timer.h"
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#include "qom/object.h"
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REG32(INTR_STATE, 0x00)
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FIELD(INTR_STATE, TX_WATERMARK, 0, 1)
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FIELD(INTR_STATE, RX_WATERMARK, 1, 1)
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FIELD(INTR_STATE, TX_EMPTY, 2, 1)
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FIELD(INTR_STATE, RX_OVERFLOW, 3, 1)
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REG32(INTR_ENABLE, 0x04)
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REG32(INTR_TEST, 0x08)
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REG32(CTRL, 0x0C)
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FIELD(CTRL, TX_ENABLE, 0, 1)
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FIELD(CTRL, RX_ENABLE, 1, 1)
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FIELD(CTRL, NF, 2, 1)
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FIELD(CTRL, SLPBK, 4, 1)
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FIELD(CTRL, LLPBK, 5, 1)
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FIELD(CTRL, PARITY_EN, 6, 1)
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FIELD(CTRL, PARITY_ODD, 7, 1)
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FIELD(CTRL, RXBLVL, 8, 2)
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FIELD(CTRL, NCO, 16, 16)
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REG32(STATUS, 0x10)
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FIELD(STATUS, TXFULL, 0, 1)
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FIELD(STATUS, RXFULL, 1, 1)
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FIELD(STATUS, TXEMPTY, 2, 1)
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FIELD(STATUS, RXIDLE, 4, 1)
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FIELD(STATUS, RXEMPTY, 5, 1)
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REG32(RDATA, 0x14)
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REG32(WDATA, 0x18)
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REG32(FIFO_CTRL, 0x1c)
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FIELD(FIFO_CTRL, RXRST, 0, 1)
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FIELD(FIFO_CTRL, TXRST, 1, 1)
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FIELD(FIFO_CTRL, RXILVL, 2, 3)
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FIELD(FIFO_CTRL, TXILVL, 5, 2)
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REG32(FIFO_STATUS, 0x20)
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FIELD(FIFO_STATUS, TXLVL, 0, 5)
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FIELD(FIFO_STATUS, RXLVL, 16, 5)
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REG32(OVRD, 0x24)
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REG32(VAL, 0x28)
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REG32(TIMEOUT_CTRL, 0x2c)
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#define IBEX_UART_TX_FIFO_SIZE 16
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#define IBEX_UART_CLOCK 50000000 /* 50MHz clock */
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@ -21,6 +21,7 @@
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#define HW_SIFIVE_UART_H
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#include "chardev/char-fe.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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@ -49,12 +50,10 @@ enum {
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#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
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#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
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#define SIFIVE_UART_RX_FIFO_SIZE 8
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#define TYPE_SIFIVE_UART "riscv.sifive.uart"
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typedef struct SiFiveUARTState SiFiveUARTState;
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DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
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TYPE_SIFIVE_UART)
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OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
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struct SiFiveUARTState {
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/*< private >*/
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@ -64,8 +63,8 @@ struct SiFiveUARTState {
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qemu_irq irq;
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MemoryRegion mmio;
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CharBackend chr;
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uint8_t rx_fifo[8];
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unsigned int rx_fifo_len;
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uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
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uint8_t rx_fifo_len;
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uint32_t ie;
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uint32_t ip;
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uint32_t txctrl;
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@ -22,6 +22,7 @@
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#include "hw/riscv/riscv_hart.h"
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#include "hw/intc/ibex_plic.h"
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#include "hw/char/ibex_uart.h"
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#include "hw/timer/ibex_timer.h"
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#include "qom/object.h"
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#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
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@ -35,6 +36,7 @@ struct LowRISCIbexSoCState {
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RISCVHartArrayState cpus;
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IbexPlicState plic;
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IbexUartState uart;
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IbexTimerState timer;
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MemoryRegion flash_mem;
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MemoryRegion rom;
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@ -57,7 +59,7 @@ enum {
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IBEX_DEV_SPI,
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IBEX_DEV_I2C,
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IBEX_DEV_PATTGEN,
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IBEX_DEV_RV_TIMER,
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IBEX_DEV_TIMER,
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IBEX_DEV_SENSOR_CTRL,
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IBEX_DEV_OTP_CTRL,
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IBEX_DEV_PWRMGR,
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@ -82,6 +84,7 @@ enum {
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};
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enum {
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IBEX_TIMER_TIMEREXPIRED0_0 = 125,
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IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
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IBEX_UART0_RX_TIMEOUT_IRQ = 7,
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IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
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52
include/hw/timer/ibex_timer.h
Normal file
52
include/hw/timer/ibex_timer.h
Normal file
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@ -0,0 +1,52 @@
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/*
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* QEMU lowRISC Ibex Timer device
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*
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* Copyright (c) 2021 Western Digital
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_IBEX_TIMER_H
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#define HW_IBEX_TIMER_H
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#include "hw/sysbus.h"
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#define TYPE_IBEX_TIMER "ibex-timer"
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OBJECT_DECLARE_SIMPLE_TYPE(IbexTimerState, IBEX_TIMER)
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struct IbexTimerState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion mmio;
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uint32_t timer_ctrl;
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uint32_t timer_cfg0;
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uint32_t timer_compare_lower0;
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uint32_t timer_compare_upper0;
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uint32_t timer_intr_enable;
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uint32_t timer_intr_state;
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uint32_t timer_intr_test;
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uint32_t timebase_freq;
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qemu_irq irq;
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};
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#endif /* HW_IBEX_TIMER_H */
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