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pull-loongarch-20230616

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Merge tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20230616

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* tag 'pull-loongarch-20230616' of https://gitlab.com/gaosong/qemu:
  target/loongarch: Fix CSR.DMW0-3.VSEG check
  hw/loongarch: Supplement cpu topology arguments
  hw/loongarch: Add numa support
  hw/intc: Set physical cpuid route for LoongArch ipi device
  hw/loongarch/virt: Add cpu arch_id support

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-06-16 12:30:16 +02:00
commit e3660cc1e3
6 changed files with 234 additions and 37 deletions
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2
target/loongarch/cpu.h
View file

@ -351,6 +351,8 @@ typedef struct CPUArchState {
MemoryRegion iocsr_mem;
bool load_elf;
uint64_t elf_address;
/* Store ipistate to access from this struct */
DeviceState *ipistate;
#endif
} CPULoongArchState;

4
target/loongarch/tlb_helper.c
View file

@ -185,10 +185,10 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
}
plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
base_v = address >> TARGET_VIRT_ADDR_SPACE_BITS;
base_v = address >> R_CSR_DMW_VSEG_SHIFT;
/* Check direct map window */
for (int i = 0; i < 4; i++) {
base_c = env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS;
base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
*physical = dmw_va2pa(address);
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;