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target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode
Add instructions of RR opcode format, that have 0x4b as the first opcode.
Add helper functions:
* parity: Calculates the parity bits for every byte of a 32 int.
* bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise.
* unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa.
* dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
where the quotient result is guaranteed to fit into 8 bit.
* dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
where the quotient result is guaranteed to fit into 16 bit.
OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Bastian Koppelmann
parent
f2f1585f60
commit
e2bed107c6
4 changed files with 390 additions and 1 deletions
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@ -1356,6 +1356,56 @@ static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
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tcg_temp_free(temp2);
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}
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static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
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{
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TCGv_i64 temp = tcg_temp_new_i64();
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gen_helper_bsplit(temp, r1);
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tcg_gen_extr_i64_i32(rl, rh, temp);
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tcg_temp_free_i64(temp);
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}
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static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
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{
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TCGv_i64 temp = tcg_temp_new_i64();
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gen_helper_unpack(temp, r1);
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tcg_gen_extr_i64_i32(rl, rh, temp);
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tcg_temp_free_i64(temp);
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}
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static inline void
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gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
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{
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TCGv_i64 ret = tcg_temp_new_i64();
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if (!tricore_feature(env, TRICORE_FEATURE_131)) {
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gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
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} else {
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gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
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}
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tcg_gen_extr_i64_i32(rl, rh, ret);
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tcg_temp_free_i64(ret);
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}
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static inline void
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gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
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{
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TCGv_i64 ret = tcg_temp_new_i64();
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if (!tricore_feature(env, TRICORE_FEATURE_131)) {
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gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
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} else {
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gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
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}
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tcg_gen_extr_i64_i32(rl, rh, ret);
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tcg_temp_free_i64(ret);
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}
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/* helpers for generating program flow micro-ops */
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static inline void gen_save_pc(target_ulong pc)
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@ -4362,6 +4412,136 @@ static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
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ctx->bstate = BS_BRANCH;
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}
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static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
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{
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uint32_t op2;
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int r1, r2, r3;
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TCGv temp, temp2;
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op2 = MASK_OP_RR_OP2(ctx->opcode);
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r3 = MASK_OP_RR_D(ctx->opcode);
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r2 = MASK_OP_RR_S2(ctx->opcode);
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r1 = MASK_OP_RR_S1(ctx->opcode);
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switch (op2) {
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case OPC2_32_RR_BMERGE:
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gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
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break;
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case OPC2_32_RR_BSPLIT:
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gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
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break;
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case OPC2_32_RR_DVINIT_B:
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gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
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cpu_gpr_d[r2]);
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break;
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case OPC2_32_RR_DVINIT_BU:
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temp = tcg_temp_new();
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temp2 = tcg_temp_new();
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/* reset av */
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tcg_gen_movi_tl(cpu_PSW_AV, 0);
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if (!tricore_feature(env, TRICORE_FEATURE_131)) {
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/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
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tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]);
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/* use cpu_PSW_AV to compare against 0 */
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tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV,
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temp, cpu_gpr_d[r3+1]);
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tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
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tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
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temp2, cpu_gpr_d[r2]);
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tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
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} else {
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/* overflow = (D[b] == 0) */
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tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
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}
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tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
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/* sv */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
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/* write result */
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tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 8);
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tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
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tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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break;
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case OPC2_32_RR_DVINIT_H:
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gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
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cpu_gpr_d[r2]);
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break;
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case OPC2_32_RR_DVINIT_HU:
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temp = tcg_temp_new();
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temp2 = tcg_temp_new();
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/* reset av */
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tcg_gen_movi_tl(cpu_PSW_AV, 0);
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if (!tricore_feature(env, TRICORE_FEATURE_131)) {
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/* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
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tcg_gen_neg_tl(temp, cpu_gpr_d[r3+1]);
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/* use cpu_PSW_AV to compare against 0 */
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tcg_gen_movcond_tl(TCG_COND_LT, temp, cpu_gpr_d[r3+1], cpu_PSW_AV,
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temp, cpu_gpr_d[r3+1]);
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tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
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tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
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temp2, cpu_gpr_d[r2]);
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tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
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} else {
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/* overflow = (D[b] == 0) */
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tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
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}
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tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
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/* sv */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
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/* write result */
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tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
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tcg_gen_shri_tl(cpu_gpr_d[r3+1], temp, 16);
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tcg_gen_shli_tl(cpu_gpr_d[r3], temp, 16);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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break;
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case OPC2_32_RR_DVINIT:
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temp = tcg_temp_new();
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temp2 = tcg_temp_new();
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/* overflow = ((D[b] == 0) ||
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((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
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tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
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tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
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tcg_gen_and_tl(temp, temp, temp2);
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tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
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tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
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tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
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/* sv */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
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/* reset av */
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tcg_gen_movi_tl(cpu_PSW_AV, 0);
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/* write result */
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tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
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/* sign extend to high reg */
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tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
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tcg_temp_free(temp);
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tcg_temp_free(temp2);
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break;
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case OPC2_32_RR_DVINIT_U:
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/* overflow = (D[b] == 0) */
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tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
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tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
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/* sv */
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tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
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/* reset av */
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tcg_gen_movi_tl(cpu_PSW_AV, 0);
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/* write result */
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tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
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/* zero extend to high reg*/
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tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
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break;
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case OPC2_32_RR_PARITY:
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gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
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break;
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case OPC2_32_RR_UNPACK:
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gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
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break;
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}
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}
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static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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{
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int op1;
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@ -4606,6 +4786,9 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
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case OPCM_32_RR_IDIRECT:
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decode_rr_idirect(env, ctx);
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break;
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case OPCM_32_RR_DIVIDE:
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decode_rr_divide(env, ctx);
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break;
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}
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}
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