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Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]

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We have found cases where pkt_has_store_s[01] is set incorrectly.
This leads to generating an unnecessary store that is left over
from a previous packet.

Add an attribute to determine if an instruction is a scalar store
The attribute is attached to the fSTORE macro (hex_common.py)
Update the logic in decode.c that sets pkt_has_store_s[01]

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220920080746.26791-4-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2022-09-20 01:07:46 -07:00
parent b772528acb
commit e2be9a5c5f
4 changed files with 17 additions and 10 deletions
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10
target/hexagon/translate.c
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@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -499,10 +499,12 @@ static void process_store_log(DisasContext *ctx, Packet *pkt)
* slot 1 and then slot 0. This will be important when
* the memory accesses overlap.
*/
if (pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa) {
if (pkt->pkt_has_store_s1) {
g_assert(!pkt->pkt_has_dczeroa);
process_store(ctx, pkt, 1);
}
if (pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa) {
if (pkt->pkt_has_store_s0) {
g_assert(!pkt->pkt_has_dczeroa);
process_store(ctx, pkt, 0);
}
}
@ -665,7 +667,7 @@ static void gen_commit_packet(CPUHexagonState *env, DisasContext *ctx,
* The dczeroa will be the store in slot 0, check that we don't have
* a store in slot 1 or an HVX store.
*/
g_assert(has_store_s0 && !has_store_s1 && !has_hvx_store);
g_assert(!has_store_s1 && !has_hvx_store);
process_dczeroa(ctx, pkt);
} else if (has_hvx_store) {
TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);