mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-02 23:33:54 -06:00
Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
We assign the instruction destination register to hex_new_value[num]
instead of a TCG temp that gets copied back to hex_new_value[num].
We introduce new functions get_result_gpr[_pair] to facilitate getting
the proper destination register.
Since we preload hex_new_value for predicated instructions, we don't
need the check for slot_cancelled. So, we call gen_log_reg_write instead.
We update the helper function generation and gen_tcg.h to maintain the
disable-hexagon-idef-parser configuration.
Here is a simple example of the differences in the TCG code generated:
IN:
0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) }
BEFORE
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
mov_i32 loc2,$0x0
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 loc2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
and_i32 tmp0,slot_cancelled,$0x8
movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq
mov_i32 r2,new_r2
AFTER
---- 00400094
mov_i32 slot_cancelled,$0x0
mov_i32 new_r2,r2
and_i32 tmp0,p0,$0x1
brcond_i32 tmp0,$0x0,eq,$L1
and_i32 tmp0,r0,r1
mov_i32 new_r2,tmp0
br $L2
set_label $L1
or_i32 slot_cancelled,slot_cancelled,$0x8
set_label $L2
mov_i32 r2,new_r2
We'll remove the unnecessary manipulation of slot_cancelled in a
subsequent patch.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson
parent
1a442c0931
commit
e28b77a6b4
8 changed files with 110 additions and 152 deletions
|
|
@ -30,23 +30,33 @@ def gen_decl_ea_tcg(f, tag):
|
|||
|
||||
def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
|
||||
regN="%s%sN" % (regtype,regid)
|
||||
f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
|
||||
(regtype, regid))
|
||||
if (regtype == "C"):
|
||||
if (regtype == "R"):
|
||||
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
|
||||
elif (regtype == "C"):
|
||||
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
|
||||
(regN, regno))
|
||||
else:
|
||||
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
f.write(" TCGv_i64 %s%sV = get_result_gpr_pair(ctx, %s);\n" % \
|
||||
(regtype, regid, regN))
|
||||
|
||||
def genptr_decl_writable(f, tag, regtype, regid, regno):
|
||||
regN="%s%sN" % (regtype,regid)
|
||||
f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
|
||||
(regtype, regid))
|
||||
if (regtype == "C"):
|
||||
if (regtype == "R"):
|
||||
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
|
||||
f.write(" TCGv %s%sV = get_result_gpr(ctx, %s);\n" % \
|
||||
(regtype, regid, regN))
|
||||
elif (regtype == "C"):
|
||||
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
|
||||
(regN, regno))
|
||||
else:
|
||||
f.write(" TCGv %s%sV = get_result_gpr(ctx, %s);\n" % \
|
||||
(regtype, regid, regN))
|
||||
elif (regtype == "P"):
|
||||
f.write(" const int %s = insn->regno[%d];\n" % (regN, regno))
|
||||
f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
|
||||
(regtype, regid))
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
|
||||
def genptr_decl(f, tag, regtype, regid, regno):
|
||||
regN="%s%sN" % (regtype,regid)
|
||||
|
|
@ -249,8 +259,12 @@ def genptr_src_read(f, tag, regtype, regid):
|
|||
f.write(" hex_gpr[%s%sN + 1]);\n" % \
|
||||
(regtype, regid))
|
||||
elif (regid in {"x", "y"}):
|
||||
f.write(" tcg_gen_mov_tl(%s%sV, hex_gpr[%s%sN]);\n" % \
|
||||
(regtype,regid,regtype,regid))
|
||||
## For read/write registers, we need to get the original value into
|
||||
## the result TCGv. For conditional instructions, this is done in
|
||||
## gen_start_packet. For unconditional instructions, we do it here.
|
||||
if ('A_CONDEXEC' not in hex_common.attribdict[tag]):
|
||||
f.write(" tcg_gen_mov_tl(%s%sV, hex_gpr[%s%sN]);\n" % \
|
||||
(regtype, regid, regtype, regid))
|
||||
elif (regid not in {"s", "t", "u", "v"}):
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
elif (regtype == "P"):
|
||||
|
|
@ -360,25 +374,16 @@ def gen_helper_call_imm(f,immlett):
|
|||
f.write(", tcgv_%s" % hex_common.imm_name(immlett))
|
||||
|
||||
def genptr_dst_write_pair(f, tag, regtype, regid):
|
||||
if ('A_CONDEXEC' in hex_common.attribdict[tag]):
|
||||
f.write(" gen_log_predicated_reg_write_pair(%s%sN, %s%sV, insn->slot);\n" % \
|
||||
(regtype, regid, regtype, regid))
|
||||
else:
|
||||
f.write(" gen_log_reg_write_pair(%s%sN, %s%sV);\n" % \
|
||||
(regtype, regid, regtype, regid))
|
||||
f.write(" gen_log_reg_write_pair(%s%sN, %s%sV);\n" % \
|
||||
(regtype, regid, regtype, regid))
|
||||
|
||||
def genptr_dst_write(f, tag, regtype, regid):
|
||||
if (regtype == "R"):
|
||||
if (regid in {"dd", "xx", "yy"}):
|
||||
genptr_dst_write_pair(f, tag, regtype, regid)
|
||||
elif (regid in {"d", "e", "x", "y"}):
|
||||
if ('A_CONDEXEC' in hex_common.attribdict[tag]):
|
||||
f.write(" gen_log_predicated_reg_write(%s%sN, %s%sV,\n" % \
|
||||
(regtype, regid, regtype, regid))
|
||||
f.write(" insn->slot);\n")
|
||||
else:
|
||||
f.write(" gen_log_reg_write(%s%sN, %s%sV);\n" % \
|
||||
(regtype, regid, regtype, regid))
|
||||
f.write(" gen_log_reg_write(%s%sN, %s%sV);\n" % \
|
||||
(regtype, regid, regtype, regid))
|
||||
else:
|
||||
print("Bad register parse: ", regtype, regid)
|
||||
elif (regtype == "P"):
|
||||
|
|
@ -462,14 +467,15 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
|
|||
## For A2_add: Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;}
|
||||
## We produce:
|
||||
## static void generate_A2_add(DisasContext *ctx)
|
||||
## {
|
||||
## TCGv RdV = tcg_temp_new();
|
||||
## const int RdN = insn->regno[0];
|
||||
## TCGv RsV = hex_gpr[insn->regno[1]];
|
||||
## TCGv RtV = hex_gpr[insn->regno[2]];
|
||||
## <GEN>
|
||||
## gen_log_reg_write(RdN, RdV);
|
||||
## }
|
||||
## {
|
||||
## Insn *insn __attribute__((unused)) = ctx->insn;
|
||||
## const int RdN = insn->regno[0];
|
||||
## TCGv RdV = get_result_gpr(ctx, RdN);
|
||||
## TCGv RsV = hex_gpr[insn->regno[1]];
|
||||
## TCGv RtV = hex_gpr[insn->regno[2]];
|
||||
## <GEN>
|
||||
## gen_log_reg_write(RdN, RdV);
|
||||
## }
|
||||
##
|
||||
## where <GEN> depends on hex_common.skip_qemu_helper(tag)
|
||||
## if hex_common.skip_qemu_helper(tag) is True
|
||||
|
|
@ -553,6 +559,14 @@ def gen_tcg_func(f, tag, regs, imms):
|
|||
if (i > 0): f.write(", ")
|
||||
f.write("cpu_env")
|
||||
i=1
|
||||
## For conditional instructions, we pass in the destination register
|
||||
if 'A_CONDEXEC' in hex_common.attribdict[tag]:
|
||||
for regtype, regid, toss, numregs in regs:
|
||||
if (hex_common.is_writeonly(regid) and
|
||||
not hex_common.is_hvx_reg(regtype)):
|
||||
gen_helper_call_opn(f, tag, regtype, regid, toss, \
|
||||
numregs, i)
|
||||
i += 1
|
||||
for regtype,regid,toss,numregs in regs:
|
||||
if (hex_common.is_written(regid)):
|
||||
if (not hex_common.is_hvx_reg(regtype)):
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue