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target/riscv: add Ventana's Veyron V1 CPU

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Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs
exclusively for the rv64 target. It's tested with the 'virt' board.

CPU specs and general information can be found here:

https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/

Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Rahul Pathak 2023-04-18 09:36:24 -03:00 • committed by Alistair Francis
parent 190e9f8ec1
commit e1d084a852
3 changed files with 43 additions and 0 deletions
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4
target/riscv/cpu_vendorid.h
View file

@ -3,4 +3,8 @@
#define THEAD_VENDOR_ID 0x5b7
#define VEYRON_V1_MARCHID 0x8000000000010000
#define VEYRON_V1_MIMPID 0x111
#define VEYRON_V1_MVENDORID 0x61f
#endif /* TARGET_RISCV_CPU_VENDORID_H */