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Per-CPU instruction decoding implementation, by Aurelien Jarno.

Browse source 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-09-24 12:48:00 +00:00
parent 92a34c10b5
commit e189e74868
6 changed files with 230 additions and 103 deletions
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9
target-mips/helper.c
View file

@ -369,8 +369,7 @@ void do_interrupt (CPUState *env)
}
enter_debug_mode:
env->hflags |= MIPS_HFLAG_DM;
if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
env->hflags |= MIPS_HFLAG_64;
env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
@ -396,8 +395,7 @@ void do_interrupt (CPUState *env)
env->CP0_ErrorEPC = env->PC[env->current_tc];
}
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
env->hflags |= MIPS_HFLAG_64;
env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
@ -499,8 +497,7 @@ void do_interrupt (CPUState *env)
env->CP0_Cause &= ~(1 << CP0Ca_BD);
}
env->CP0_Status |= (1 << CP0St_EXL);
if ((env->CP0_Config0 & (0x3 << CP0C0_AT)))
env->hflags |= MIPS_HFLAG_64;
env->hflags |= MIPS_HFLAG_64;
env->hflags &= ~MIPS_HFLAG_UM;
}
env->hflags &= ~MIPS_HFLAG_BMASK;