motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-06 09:13:55 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: Add Zvbc ISA extension support

Browse source 
This commit adds support for the Zvbc vector-crypto extension, which
consists of the following instructions:

* vclmulh.[vx,vv]
* vclmul.[vx,vv]

Translation functions are defined in
`target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in
`target/riscv/vcrypto_helper.c`.

Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Co-authored-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Signed-off-by: Max Chou <max.chou@sifive.com>
[max.chou@sifive.com: Exposed x-zvbc property]
Message-ID: <20230711165917.2629866-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Lawrence Hunter 2023-07-12 00:59:03 +08:00 • committed by Alistair Francis
parent 922f873511
commit e13c7d3b5b
8 changed files with 146 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

62
target/riscv/insn_trans/trans_rvvk.c.inc Normal file
View file

@ -0,0 +1,62 @@
/*
* RISC-V translation routines for the vector crypto extension.
*
* Copyright (C) 2023 SiFive, Inc.
* Written by Codethink Ltd and SiFive.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Zvbc
*/
#define GEN_VV_MASKED_TRANS(NAME, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
if (CHECK(s, a)) { \
return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \
gen_helper_##NAME, s); \
} \
return false; \
}
static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a)
{
return opivv_check(s, a) &&
s->cfg_ptr->ext_zvbc == true &&
s->sew == MO_64;
}
GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check)
GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check)
#define GEN_VX_MASKED_TRANS(NAME, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \
if (CHECK(s, a)) { \
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \
gen_helper_##NAME, s); \
} \
return false; \
}
static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
{
return opivx_check(s, a) &&
s->cfg_ptr->ext_zvbc == true &&
s->sew == MO_64;
}
GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)