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target/riscv: add support for Zcb extension

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Add encode and trans* functions support for Zcb instructions.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-6-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-07 16:13:58 +08:00 • committed by Alistair Francis
parent c4935b5842
commit e0a3054f18
3 changed files with 125 additions and 0 deletions
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100
target/riscv/insn_trans/trans_rvzce.c.inc Normal file
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/*
* RISC-V translation routines for the Zcb Standard Extension.
*
* Copyright (c) 2021-2022 PLCT Lab
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define REQUIRE_ZCB(ctx) do { \
if (!ctx->cfg_ptr->ext_zcb) \
return false; \
} while (0)
static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a)
{
REQUIRE_ZCB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8u_tl);
}
static bool trans_c_zext_h(DisasContext *ctx, arg_c_zext_h *a)
{
REQUIRE_ZCB(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
}
static bool trans_c_sext_b(DisasContext *ctx, arg_c_sext_b *a)
{
REQUIRE_ZCB(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
}
static bool trans_c_sext_h(DisasContext *ctx, arg_c_sext_h *a)
{
REQUIRE_ZCB(ctx);
REQUIRE_ZBB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
}
static bool trans_c_zext_w(DisasContext *ctx, arg_c_zext_w *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZCB(ctx);
REQUIRE_ZBA(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext32u_tl);
}
static bool trans_c_not(DisasContext *ctx, arg_c_not *a)
{
REQUIRE_ZCB(ctx);
return gen_unary(ctx, a, EXT_NONE, tcg_gen_not_tl);
}
static bool trans_c_mul(DisasContext *ctx, arg_c_mul *a)
{
REQUIRE_ZCB(ctx);
REQUIRE_M_OR_ZMMUL(ctx);
return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL);
}
static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a)
{
REQUIRE_ZCB(ctx);
return gen_load(ctx, a, MO_UB);
}
static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a)
{
REQUIRE_ZCB(ctx);
return gen_load(ctx, a, MO_UW);
}
static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a)
{
REQUIRE_ZCB(ctx);
return gen_load(ctx, a, MO_SW);
}
static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a)
{
REQUIRE_ZCB(ctx);
return gen_store(ctx, a, MO_UB);
}
static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
{
REQUIRE_ZCB(ctx);
return gen_store(ctx, a, MO_UW);
}