tests/tcg: refine MMX support in SSE tests

Extend the support to memory operands, and skip MMX instructions that
were introduced in SSE times, because they are now covered in test-mmx.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2022-09-09 10:21:31 +02:00
parent fa7ce0b028
commit e02907cc12

View file

@ -103,7 +103,11 @@ class XMMArg():
class MMArg(): class MMArg():
isxmm = True isxmm = True
ismem = False # TODO def __init__(self, mw):
if mw not in [0, 32, 64]:
raise Exception("Bad mem width: %s" % mw)
self.mw = mw
self.ismem = mw != 0
def regstr(self, n): def regstr(self, n):
return "mm%d" % (n & 7) return "mm%d" % (n & 7)
@ -169,6 +173,9 @@ class ArgMem():
def regstr(self, n): def regstr(self, n):
return mem_w(self.w) return mem_w(self.w)
class SkipInstruction(Exception):
pass
def ArgGenerator(arg, op): def ArgGenerator(arg, op):
if arg[:3] == 'xmm' or arg[:3] == "ymm": if arg[:3] == 'xmm' or arg[:3] == "ymm":
if "/" in arg: if "/" in arg:
@ -179,7 +186,13 @@ def ArgGenerator(arg, op):
else: else:
return XMMArg(arg[0], 0); return XMMArg(arg[0], 0);
elif arg[:2] == 'mm': elif arg[:2] == 'mm':
return MMArg(); if "/" in arg:
r, m = arg.split('/')
if (m[0] != 'm'):
raise Exception("Expected /m: %s", arg)
return MMArg(int(m[1:]));
else:
return MMArg(0);
elif arg[:4] == 'imm8': elif arg[:4] == 'imm8':
return ArgImm8u(op); return ArgImm8u(op);
elif arg == '<XMM0>': elif arg == '<XMM0>':
@ -217,8 +230,12 @@ class InsnGenerator:
try: try:
self.args = list(ArgGenerator(a, op) for a in args) self.args = list(ArgGenerator(a, op) for a in args)
if not any((x.isxmm for x in self.args)):
raise SkipInstruction
if len(self.args) > 0 and self.args[-1] is None: if len(self.args) > 0 and self.args[-1] is None:
self.args = self.args[:-1] self.args = self.args[:-1]
except SkipInstruction:
raise
except Exception as e: except Exception as e:
raise Exception("Bad arg %s: %s" % (op, e)) raise Exception("Bad arg %s: %s" % (op, e))
@ -339,10 +356,13 @@ def main():
continue continue
cpuid = row[6] cpuid = row[6]
if cpuid in archs: if cpuid in archs:
g = InsnGenerator(insn[0], insn[1:]) try:
for insn in g.gen(): g = InsnGenerator(insn[0], insn[1:])
outf.write('TEST(%d, "%s", %s)\n' % (n, insn, g.optype)) for insn in g.gen():
n += 1 outf.write('TEST(%d, "%s", %s)\n' % (n, insn, g.optype))
n += 1
except SkipInstruction:
pass
outf.write("#undef TEST\n") outf.write("#undef TEST\n")
csvfile.close() csvfile.close()