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target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2

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This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.

Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-02-07 14:04:23 +00:00 • committed by Peter Maydell
parent 127b2b0863
commit e013b74113
4 changed files with 15 additions and 15 deletions
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4
target/arm/cpu.h
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@ -2907,7 +2907,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
typedef enum ARMMMUIdx {
ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
ARMMMUIdx_E10_1 = 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_SE3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_0 = 4 | ARM_MMU_IDX_A,
ARMMMUIdx_SE10_1 = 5 | ARM_MMU_IDX_A,
@ -2933,7 +2933,7 @@ typedef enum ARMMMUIdx {
typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_E10_0 = 1 << 0,
ARMMMUIdxBit_E10_1 = 1 << 1,
ARMMMUIdxBit_S1E2 = 1 << 2,
ARMMMUIdxBit_E2 = 1 << 2,
ARMMMUIdxBit_SE3 = 1 << 3,
ARMMMUIdxBit_SE10_0 = 1 << 4,
ARMMMUIdxBit_SE10_1 = 1 << 5,