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fw_cfg: add dma interface, add strings via cmdline.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJWJdomAAoJEEy22O7T6HE4wPoQALST6AWh/3Ki1SVwMyP5KUru bqfII25LDhRNgoyeCA4/LrKhJJC296uO7+/eUOByHIEEb8mWjfHucPCd7ZTsYwHI 9zQCL6MgnVzjiM5bDBP//1b69mLDQgDCV15QNZHiuYbKhhy/nv8MGqvb9RrpKf9U gDy9aYEFugicWxb5t1rZjxRKCsJkOxOZXEw+CuIEDL1jxQNOsFaMNIkvuoCSRSxK 783Lr9oZDpbPcTOl3dlu6iOJsXkDxgLuntEH/TcczmgZWxnNTPRjcgMXjznGYUed JPIbUb/AkUrN9dJNF6zaA99N8S6f57WVLalaViT7oBX1p1OcbK36nS2Jt54D9Tqy LTeu2D/jcp5bGciA2uVKVgHTm2IvN5Igl3mndK4RRIXJ6kJ3nrFRz8mahlkVNHFP YsmOapccsuSbS3u6rcjtLsSAQXJbLWPve579Eo/i6mbyYEzqF12eET2vMbYHOEil 8s4BtdWnQKpCRQSc0i8MyEy4Uylrx9UhXMhnWSsbJvyI/PkOxD9Zfo1RB8ClTsKS WV3vhhOJkEciN4ebMs60Vgm8cDYkgMG/Tt6boczl4ATihUtsD4EX4db9ZebwVCJT 9Or+mBDSZzYFkWZPmIZmh5bXbjyYIe6azTJjIvjz4UTmPuZONPl5WgwDbazH+v0Q Lsb4wkHwXsg7bwihlJdL =deAj -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/kraxel/tags/pull-fw_cfg-20151020-1' into staging fw_cfg: add dma interface, add strings via cmdline. # gpg: Signature made Tue 20 Oct 2015 07:07:34 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-fw_cfg-20151020-1: fw_cfg: Define a static signature to be returned on DMA port reads Enable fw_cfg DMA interface for x86 Enable fw_cfg DMA interface for ARM Implement fw_cfg DMA interface fw_cfg DMA interface documentation fw_cfg: document fw_cfg_modify_iXX() update functions fw_cfg: insert string blobs via qemu cmdline Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
df81978368
8 changed files with 389 additions and 33 deletions
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@ -119,7 +119,7 @@ static const MemMapEntry a15memmap[] = {
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[VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
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[VIRT_UART] = { 0x09000000, 0x00001000 },
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[VIRT_RTC] = { 0x09010000, 0x00001000 },
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[VIRT_FW_CFG] = { 0x09020000, 0x0000000a },
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[VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
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[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
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/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
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[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
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@ -677,13 +677,13 @@ static void create_flash(const VirtBoardInfo *vbi)
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g_free(nodename);
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}
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static void create_fw_cfg(const VirtBoardInfo *vbi)
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static void create_fw_cfg(const VirtBoardInfo *vbi, AddressSpace *as)
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{
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hwaddr base = vbi->memmap[VIRT_FW_CFG].base;
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hwaddr size = vbi->memmap[VIRT_FW_CFG].size;
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char *nodename;
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fw_cfg_init_mem_wide(base + 8, base, 8);
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fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
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nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
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qemu_fdt_add_subnode(vbi->fdt, nodename);
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@ -1031,7 +1031,7 @@ static void machvirt_init(MachineState *machine)
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*/
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create_virtio_devices(vbi, pic);
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create_fw_cfg(vbi);
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create_fw_cfg(vbi, &address_space_memory);
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rom_set_fw(fw_cfg_find());
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guest_info->smp_cpus = smp_cpus;
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@ -752,14 +752,15 @@ static void pc_build_smbios(FWCfgState *fw_cfg)
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}
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}
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static FWCfgState *bochs_bios_init(void)
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static FWCfgState *bochs_bios_init(AddressSpace *as)
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{
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FWCfgState *fw_cfg;
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uint64_t *numa_fw_cfg;
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int i, j;
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unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
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fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT);
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fw_cfg = fw_cfg_init_io_dma(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 4, as);
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/* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86:
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*
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* SeaBIOS needs FW_CFG_MAX_CPUS for CPU hotplug, but the CPU hotplug
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@ -1393,7 +1394,8 @@ FWCfgState *pc_memory_init(PCMachineState *pcms,
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option_rom_mr,
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1);
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fw_cfg = bochs_bios_init();
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fw_cfg = bochs_bios_init(&address_space_memory);
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rom_set_fw(fw_cfg);
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if (guest_info->has_reserved_memory && pcms->hotplug_memory.base) {
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@ -23,6 +23,7 @@
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*/
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#include "hw/hw.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/dma.h"
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#include "hw/isa/isa.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/sysbus.h"
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@ -30,7 +31,7 @@
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#include "qemu/error-report.h"
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#include "qemu/config-file.h"
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#define FW_CFG_SIZE 2
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#define FW_CFG_CTL_SIZE 2
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#define FW_CFG_NAME "fw_cfg"
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#define FW_CFG_PATH "/machine/" FW_CFG_NAME
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@ -42,6 +43,18 @@
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#define FW_CFG_IO(obj) OBJECT_CHECK(FWCfgIoState, (obj), TYPE_FW_CFG_IO)
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#define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_MEM)
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/* FW_CFG_VERSION bits */
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#define FW_CFG_VERSION 0x01
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#define FW_CFG_VERSION_DMA 0x02
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/* FW_CFG_DMA_CONTROL bits */
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#define FW_CFG_DMA_CTL_ERROR 0x01
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#define FW_CFG_DMA_CTL_READ 0x02
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#define FW_CFG_DMA_CTL_SKIP 0x04
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#define FW_CFG_DMA_CTL_SELECT 0x08
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#define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
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typedef struct FWCfgEntry {
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uint32_t len;
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uint8_t *data;
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@ -59,6 +72,11 @@ struct FWCfgState {
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uint16_t cur_entry;
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uint32_t cur_offset;
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Notifier machine_ready;
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bool dma_enabled;
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dma_addr_t dma_addr;
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AddressSpace *dma_as;
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MemoryRegion dma_iomem;
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};
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struct FWCfgIoState {
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@ -67,7 +85,7 @@ struct FWCfgIoState {
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/*< public >*/
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MemoryRegion comb_iomem;
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uint32_t iobase;
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uint32_t iobase, dma_iobase;
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};
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struct FWCfgMemState {
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@ -292,6 +310,129 @@ static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
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} while (i);
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}
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static void fw_cfg_dma_transfer(FWCfgState *s)
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{
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dma_addr_t len;
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FWCfgDmaAccess dma;
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int arch;
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FWCfgEntry *e;
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int read;
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dma_addr_t dma_addr;
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/* Reset the address before the next access */
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dma_addr = s->dma_addr;
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s->dma_addr = 0;
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if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) {
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stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
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FW_CFG_DMA_CTL_ERROR);
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return;
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}
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dma.address = be64_to_cpu(dma.address);
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dma.length = be32_to_cpu(dma.length);
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dma.control = be32_to_cpu(dma.control);
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if (dma.control & FW_CFG_DMA_CTL_SELECT) {
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fw_cfg_select(s, dma.control >> 16);
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}
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arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
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e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
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if (dma.control & FW_CFG_DMA_CTL_READ) {
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read = 1;
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} else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
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read = 0;
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} else {
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dma.length = 0;
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}
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dma.control = 0;
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while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
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if (s->cur_entry == FW_CFG_INVALID || !e->data ||
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s->cur_offset >= e->len) {
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len = dma.length;
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/* If the access is not a read access, it will be a skip access,
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* tested before.
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*/
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if (read) {
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if (dma_memory_set(s->dma_as, dma.address, 0, len)) {
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dma.control |= FW_CFG_DMA_CTL_ERROR;
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}
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}
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} else {
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if (dma.length <= (e->len - s->cur_offset)) {
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len = dma.length;
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} else {
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len = (e->len - s->cur_offset);
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}
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if (e->read_callback) {
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e->read_callback(e->callback_opaque, s->cur_offset);
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}
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/* If the access is not a read access, it will be a skip access,
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* tested before.
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*/
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if (read) {
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if (dma_memory_write(s->dma_as, dma.address,
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&e->data[s->cur_offset], len)) {
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dma.control |= FW_CFG_DMA_CTL_ERROR;
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}
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}
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s->cur_offset += len;
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}
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dma.address += len;
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dma.length -= len;
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}
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stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
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dma.control);
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trace_fw_cfg_read(s, 0);
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}
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static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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/* Return a signature value (and handle various read sizes) */
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return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
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}
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static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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FWCfgState *s = opaque;
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if (size == 4) {
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if (addr == 0) {
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/* FWCfgDmaAccess high address */
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s->dma_addr = value << 32;
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} else if (addr == 4) {
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/* FWCfgDmaAccess low address */
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s->dma_addr |= value;
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fw_cfg_dma_transfer(s);
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}
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} else if (size == 8 && addr == 0) {
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s->dma_addr = value;
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fw_cfg_dma_transfer(s);
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}
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}
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static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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{
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return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
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(size == 8 && addr == 0));
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}
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static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
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unsigned size, bool is_write)
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{
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@ -359,6 +500,15 @@ static const MemoryRegionOps fw_cfg_comb_mem_ops = {
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.valid.accepts = fw_cfg_comb_valid,
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};
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static const MemoryRegionOps fw_cfg_dma_mem_ops = {
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.read = fw_cfg_dma_mem_read,
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.write = fw_cfg_dma_mem_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid.accepts = fw_cfg_dma_mem_valid,
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.valid.max_access_size = 8,
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.impl.max_access_size = 8,
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};
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static void fw_cfg_reset(DeviceState *d)
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{
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FWCfgState *s = FW_CFG(d);
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@ -399,6 +549,22 @@ static bool is_version_1(void *opaque, int version_id)
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return version_id == 1;
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}
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static bool fw_cfg_dma_enabled(void *opaque)
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{
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FWCfgState *s = opaque;
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return s->dma_enabled;
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}
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static const VMStateDescription vmstate_fw_cfg_dma = {
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.name = "fw_cfg/dma",
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.needed = fw_cfg_dma_enabled,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(dma_addr, FWCfgState),
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VMSTATE_END_OF_LIST()
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},
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};
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static const VMStateDescription vmstate_fw_cfg = {
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.name = "fw_cfg",
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.version_id = 2,
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@ -408,6 +574,10 @@ static const VMStateDescription vmstate_fw_cfg = {
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VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
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VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_fw_cfg_dma,
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NULL,
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}
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};
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@ -593,7 +763,6 @@ static void fw_cfg_init1(DeviceState *dev)
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qdev_init_nofail(dev);
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fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
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fw_cfg_add_i32(s, FW_CFG_ID, 1);
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fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
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fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));
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fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
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@ -605,25 +774,53 @@ static void fw_cfg_init1(DeviceState *dev)
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qemu_add_machine_init_done_notifier(&s->machine_ready);
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}
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FWCfgState *fw_cfg_init_io(uint32_t iobase)
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FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
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AddressSpace *dma_as)
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{
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DeviceState *dev;
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FWCfgState *s;
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uint32_t version = FW_CFG_VERSION;
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bool dma_enabled = dma_iobase && dma_as;
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dev = qdev_create(NULL, TYPE_FW_CFG_IO);
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qdev_prop_set_uint32(dev, "iobase", iobase);
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fw_cfg_init1(dev);
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qdev_prop_set_uint32(dev, "dma_iobase", dma_iobase);
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qdev_prop_set_bit(dev, "dma_enabled", dma_enabled);
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return FW_CFG(dev);
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fw_cfg_init1(dev);
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s = FW_CFG(dev);
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if (dma_enabled) {
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/* 64 bits for the address field */
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s->dma_as = dma_as;
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s->dma_addr = 0;
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version |= FW_CFG_VERSION_DMA;
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}
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fw_cfg_add_i32(s, FW_CFG_ID, version);
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return s;
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}
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FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, hwaddr data_addr,
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uint32_t data_width)
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FWCfgState *fw_cfg_init_io(uint32_t iobase)
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{
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return fw_cfg_init_io_dma(iobase, 0, NULL);
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}
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FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
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hwaddr data_addr, uint32_t data_width,
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hwaddr dma_addr, AddressSpace *dma_as)
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{
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DeviceState *dev;
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SysBusDevice *sbd;
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FWCfgState *s;
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uint32_t version = FW_CFG_VERSION;
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bool dma_enabled = dma_addr && dma_as;
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dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
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qdev_prop_set_uint32(dev, "data_width", data_width);
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qdev_prop_set_bit(dev, "dma_enabled", dma_enabled);
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fw_cfg_init1(dev);
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@ -631,13 +828,25 @@ FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, hwaddr data_addr,
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sysbus_mmio_map(sbd, 0, ctl_addr);
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sysbus_mmio_map(sbd, 1, data_addr);
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return FW_CFG(dev);
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s = FW_CFG(dev);
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if (dma_enabled) {
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s->dma_as = dma_as;
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s->dma_addr = 0;
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sysbus_mmio_map(sbd, 2, dma_addr);
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version |= FW_CFG_VERSION_DMA;
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}
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fw_cfg_add_i32(s, FW_CFG_ID, version);
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return s;
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}
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FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
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{
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return fw_cfg_init_mem_wide(ctl_addr, data_addr,
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fw_cfg_data_mem_ops.valid.max_access_size);
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fw_cfg_data_mem_ops.valid.max_access_size,
|
||||
0, NULL);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -664,6 +873,9 @@ static const TypeInfo fw_cfg_info = {
|
|||
|
||||
static Property fw_cfg_io_properties[] = {
|
||||
DEFINE_PROP_UINT32("iobase", FWCfgIoState, iobase, -1),
|
||||
DEFINE_PROP_UINT32("dma_iobase", FWCfgIoState, dma_iobase, -1),
|
||||
DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
|
||||
false),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
|
|
@ -673,8 +885,15 @@ static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
|
|||
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
||||
|
||||
memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
|
||||
FW_CFG(s), "fwcfg", FW_CFG_SIZE);
|
||||
FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
|
||||
sysbus_add_io(sbd, s->iobase, &s->comb_iomem);
|
||||
|
||||
if (FW_CFG(s)->dma_enabled) {
|
||||
memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
|
||||
&fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
|
||||
sizeof(dma_addr_t));
|
||||
sysbus_add_io(sbd, s->dma_iobase, &FW_CFG(s)->dma_iomem);
|
||||
}
|
||||
}
|
||||
|
||||
static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
|
||||
|
|
@ -695,6 +914,8 @@ static const TypeInfo fw_cfg_io_info = {
|
|||
|
||||
static Property fw_cfg_mem_properties[] = {
|
||||
DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
|
||||
DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
|
||||
false),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
};
|
||||
|
||||
|
|
@ -705,7 +926,7 @@ static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
|
|||
const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
|
||||
|
||||
memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
|
||||
FW_CFG(s), "fwcfg.ctl", FW_CFG_SIZE);
|
||||
FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
|
||||
sysbus_init_mmio(sbd, &s->ctl_iomem);
|
||||
|
||||
if (s->data_width > data_ops->valid.max_access_size) {
|
||||
|
|
@ -723,6 +944,13 @@ static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
|
|||
memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
|
||||
"fwcfg.data", data_ops->valid.max_access_size);
|
||||
sysbus_init_mmio(sbd, &s->data_iomem);
|
||||
|
||||
if (FW_CFG(s)->dma_enabled) {
|
||||
memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
|
||||
&fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
|
||||
sizeof(dma_addr_t));
|
||||
sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
|
||||
}
|
||||
}
|
||||
|
||||
static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue