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https://github.com/Motorhead1991/qemu.git
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cpu: Split as cpu-common / cpu-sysemu
The current cpu.c contains sysemu-specific methods. To avoid building them in user-mode builds, split the current cpu.c as cpu-common.c / cpu-sysemu.c. Start by moving cpu_get_crash_info(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
Richard Henderson
parent
046943acf4
commit
df4fd7d5c8
3 changed files with 36 additions and 18 deletions
420
hw/core/cpu-common.c
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420
hw/core/cpu-common.c
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/*
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* QEMU CPU model
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*
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* Copyright (c) 2012-2014 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/core/cpu.h"
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#include "sysemu/hw_accel.h"
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#include "qemu/notify.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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#include "exec/log.h"
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#include "exec/cpu-common.h"
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#include "qemu/error-report.h"
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#include "qemu/qemu-print.h"
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#include "sysemu/tcg.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "trace/trace-root.h"
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#include "qemu/plugin.h"
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CPUState *cpu_by_arch_id(int64_t id)
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{
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CPUState *cpu;
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CPU_FOREACH(cpu) {
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (cc->get_arch_id(cpu) == id) {
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return cpu;
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}
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}
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return NULL;
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}
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bool cpu_exists(int64_t id)
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{
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return !!cpu_by_arch_id(id);
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}
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CPUState *cpu_create(const char *typename)
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{
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Error *err = NULL;
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CPUState *cpu = CPU(object_new(typename));
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if (!qdev_realize(DEVICE(cpu), NULL, &err)) {
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error_report_err(err);
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object_unref(OBJECT(cpu));
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exit(EXIT_FAILURE);
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}
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return cpu;
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}
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bool cpu_paging_enabled(const CPUState *cpu)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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return cc->get_paging_enabled(cpu);
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}
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static bool cpu_common_get_paging_enabled(const CPUState *cpu)
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{
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return false;
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}
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void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
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Error **errp)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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cc->get_memory_mapping(cpu, list, errp);
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}
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static void cpu_common_get_memory_mapping(CPUState *cpu,
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MemoryMappingList *list,
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Error **errp)
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{
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error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
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}
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/* Resetting the IRQ comes from across the code base so we take the
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* BQL here if we need to. cpu_interrupt assumes it is held.*/
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void cpu_reset_interrupt(CPUState *cpu, int mask)
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{
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bool need_lock = !qemu_mutex_iothread_locked();
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if (need_lock) {
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qemu_mutex_lock_iothread();
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}
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cpu->interrupt_request &= ~mask;
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if (need_lock) {
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qemu_mutex_unlock_iothread();
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}
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}
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void cpu_exit(CPUState *cpu)
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{
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qatomic_set(&cpu->exit_request, 1);
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/* Ensure cpu_exec will see the exit request after TCG has exited. */
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smp_wmb();
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qatomic_set(&cpu->icount_decr_ptr->u16.high, -1);
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}
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int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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return (*cc->write_elf32_qemunote)(f, cpu, opaque);
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}
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static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
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CPUState *cpu, void *opaque)
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{
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return 0;
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}
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int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
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}
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static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
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CPUState *cpu, int cpuid,
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void *opaque)
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{
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return -1;
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}
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int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
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void *opaque)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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return (*cc->write_elf64_qemunote)(f, cpu, opaque);
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}
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static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
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CPUState *cpu, void *opaque)
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{
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return 0;
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}
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int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
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int cpuid, void *opaque)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
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}
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static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
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CPUState *cpu, int cpuid,
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void *opaque)
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{
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return -1;
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}
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static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
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{
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return 0;
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}
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static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
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{
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return 0;
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}
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static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
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{
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return target_words_bigendian();
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}
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void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (cc->dump_state) {
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cpu_synchronize_state(cpu);
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cc->dump_state(cpu, f, flags);
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}
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}
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void cpu_dump_statistics(CPUState *cpu, int flags)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (cc->dump_statistics) {
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cc->dump_statistics(cpu, flags);
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}
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}
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void cpu_reset(CPUState *cpu)
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{
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device_cold_reset(DEVICE(cpu));
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trace_guest_cpu_reset(cpu);
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}
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static void cpu_common_reset(DeviceState *dev)
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{
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CPUState *cpu = CPU(dev);
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
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log_cpu_state(cpu, cc->reset_dump_flags);
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}
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cpu->interrupt_request = 0;
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cpu->halted = cpu->start_powered_off;
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cpu->mem_io_pc = 0;
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cpu->icount_extra = 0;
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qatomic_set(&cpu->icount_decr_ptr->u32, 0);
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cpu->can_do_io = 1;
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cpu->exception_index = -1;
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cpu->crash_occurred = false;
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cpu->cflags_next_tb = -1;
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if (tcg_enabled()) {
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cpu_tb_jmp_cache_clear(cpu);
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tcg_flush_softmmu_tlb(cpu);
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}
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}
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static bool cpu_common_has_work(CPUState *cs)
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{
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return false;
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}
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ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
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{
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CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
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assert(cpu_model && cc->class_by_name);
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return cc->class_by_name(cpu_model);
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}
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static void cpu_common_parse_features(const char *typename, char *features,
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Error **errp)
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{
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char *val;
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static bool cpu_globals_initialized;
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/* Single "key=value" string being parsed */
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char *featurestr = features ? strtok(features, ",") : NULL;
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/* should be called only once, catch invalid users */
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assert(!cpu_globals_initialized);
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cpu_globals_initialized = true;
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while (featurestr) {
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val = strchr(featurestr, '=');
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if (val) {
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GlobalProperty *prop = g_new0(typeof(*prop), 1);
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*val = 0;
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val++;
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prop->driver = typename;
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prop->property = g_strdup(featurestr);
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prop->value = g_strdup(val);
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qdev_prop_register_global(prop);
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} else {
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error_setg(errp, "Expected key=value format, found %s.",
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featurestr);
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return;
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}
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featurestr = strtok(NULL, ",");
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}
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}
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static void cpu_common_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cpu = CPU(dev);
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Object *machine = qdev_get_machine();
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/* qdev_get_machine() can return something that's not TYPE_MACHINE
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* if this is one of the user-only emulators; in that case there's
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* no need to check the ignore_memory_transaction_failures board flag.
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*/
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if (object_dynamic_cast(machine, TYPE_MACHINE)) {
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ObjectClass *oc = object_get_class(machine);
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MachineClass *mc = MACHINE_CLASS(oc);
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if (mc) {
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cpu->ignore_memory_transaction_failures =
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mc->ignore_memory_transaction_failures;
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}
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}
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if (dev->hotplugged) {
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cpu_synchronize_post_init(cpu);
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cpu_resume(cpu);
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}
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/* NOTE: latest generic point where the cpu is fully realized */
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trace_init_vcpu(cpu);
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}
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static void cpu_common_unrealizefn(DeviceState *dev)
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{
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CPUState *cpu = CPU(dev);
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/* NOTE: latest generic point before the cpu is fully unrealized */
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trace_fini_vcpu(cpu);
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cpu_exec_unrealizefn(cpu);
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}
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static void cpu_common_initfn(Object *obj)
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{
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CPUState *cpu = CPU(obj);
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CPUClass *cc = CPU_GET_CLASS(obj);
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cpu->cpu_index = UNASSIGNED_CPU_INDEX;
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cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
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cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
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/* *-user doesn't have configurable SMP topology */
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/* the default value is changed by qemu_init_vcpu() for softmmu */
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cpu->nr_cores = 1;
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cpu->nr_threads = 1;
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qemu_mutex_init(&cpu->work_mutex);
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QSIMPLEQ_INIT(&cpu->work_list);
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QTAILQ_INIT(&cpu->breakpoints);
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QTAILQ_INIT(&cpu->watchpoints);
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cpu_exec_initfn(cpu);
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}
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static void cpu_common_finalize(Object *obj)
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{
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CPUState *cpu = CPU(obj);
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qemu_mutex_destroy(&cpu->work_mutex);
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}
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static int64_t cpu_common_get_arch_id(CPUState *cpu)
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{
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return cpu->cpu_index;
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}
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static Property cpu_common_props[] = {
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#ifndef CONFIG_USER_ONLY
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/* Create a memory property for softmmu CPU object,
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* so users can wire up its memory. (This can't go in hw/core/cpu.c
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* because that file is compiled only once for both user-mode
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* and system builds.) The default if no link is set up is to use
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* the system address space.
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*/
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DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
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MemoryRegion *),
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#endif
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DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void cpu_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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CPUClass *k = CPU_CLASS(klass);
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k->parse_features = cpu_common_parse_features;
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k->get_arch_id = cpu_common_get_arch_id;
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k->has_work = cpu_common_has_work;
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k->get_paging_enabled = cpu_common_get_paging_enabled;
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k->get_memory_mapping = cpu_common_get_memory_mapping;
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k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
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k->write_elf32_note = cpu_common_write_elf32_note;
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k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
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k->write_elf64_note = cpu_common_write_elf64_note;
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k->gdb_read_register = cpu_common_gdb_read_register;
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k->gdb_write_register = cpu_common_gdb_write_register;
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k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
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set_bit(DEVICE_CATEGORY_CPU, dc->categories);
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dc->realize = cpu_common_realizefn;
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dc->unrealize = cpu_common_unrealizefn;
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dc->reset = cpu_common_reset;
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device_class_set_props(dc, cpu_common_props);
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/*
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* Reason: CPUs still need special care by board code: wiring up
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* IRQs, adding reset handlers, halting non-first CPUs, ...
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo cpu_type_info = {
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.name = TYPE_CPU,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CPUState),
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.instance_init = cpu_common_initfn,
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.instance_finalize = cpu_common_finalize,
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.abstract = true,
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.class_size = sizeof(CPUClass),
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.class_init = cpu_class_init,
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};
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static void cpu_register_types(void)
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{
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type_register_static(&cpu_type_info);
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}
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type_init(cpu_register_types)
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