mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-09 10:34:58 -06:00
Merge remote-tracking branch 'upstream' into memory/batch
* upstream: (87 commits) target-alpha: Fix compilation errors for 32 bit hosts target-alpha: Add high-resolution access to wall clock and an alarm. target-alpha: Implement HALT IPR. target-alpha: Implement WAIT IPR. target-alpha: Add CLIPPER emulation. target-alpha: Add custom PALcode image for CLIPPER emulation. target-alpha: Honor icount for RPCC instruction. tcg/s390: Remove unused tcg_out_addi() tcg/ia64: Remove unused tcg_out_addi() ARM: fix segfault ppc64: Fix linker script pseries: Implement set-time-of-day RTAS function pseries: Refactor spapr irq allocation PPC: Clean up BookE timer code PPC: booke timers KVM: PPC: Use HIOR setting for -M pseries with PR KVM KVM: Update kernel headers KVM: Update kernel headers PPC: Fix heathrow PIC to use little endian MMIO PPC: Fix via-cuda memory registration ... Conflicts: hw/milkymist-uart.c hw/ppce500_mpc8544ds.c Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity
commit
df2921d326
78 changed files with 3467 additions and 661 deletions
291
hw/openpic.c
291
hw/openpic.c
|
|
@ -2,6 +2,7 @@
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|||
* OpenPIC emulation
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*
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* Copyright (c) 2004 Jocelyn Mayer
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* 2011 Alexander Graf
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -56,13 +57,13 @@
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#define MAX_MBX 4
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#define MAX_TMR 4
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#define VECTOR_BITS 8
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#define MAX_IPI 0
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#define MAX_IPI 4
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#define VID (0x00000000)
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#elif defined(USE_MPCxxx)
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#define MAX_CPU 2
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#define MAX_CPU 15
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#define MAX_IRQ 128
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#define MAX_DBL 0
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#define MAX_MBX 0
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@ -127,14 +128,14 @@ enum {
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#define MPIC_MSI_REG_START 0x11C00
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#define MPIC_MSI_REG_SIZE 0x100
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#define MPIC_CPU_REG_START 0x20000
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#define MPIC_CPU_REG_SIZE 0x100
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#define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
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enum mpic_ide_bits {
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IDR_EP = 0,
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IDR_CI0 = 1,
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IDR_CI1 = 2,
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IDR_P1 = 30,
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IDR_P0 = 31,
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IDR_EP = 31,
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IDR_CI0 = 30,
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IDR_CI1 = 29,
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IDR_P1 = 1,
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IDR_P0 = 0,
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};
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#else
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@ -161,6 +162,16 @@ static inline int test_bit (uint32_t *field, int bit)
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return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
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}
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static int get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
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int idx);
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static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
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uint32_t val, int idx);
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enum {
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IRQ_EXTERNAL = 0x01,
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IRQ_INTERNAL = 0x02,
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@ -465,46 +476,35 @@ static void openpic_reset (void *opaque)
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opp->glbc = 0x00000000;
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}
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static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
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static inline uint32_t read_IRQreg_ide(openpic_t *opp, int n_IRQ)
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{
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uint32_t retval;
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switch (reg) {
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case IRQ_IPVP:
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retval = opp->src[n_IRQ].ipvp;
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break;
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case IRQ_IDE:
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retval = opp->src[n_IRQ].ide;
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break;
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}
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return retval;
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return opp->src[n_IRQ].ide;
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}
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static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
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uint32_t reg, uint32_t val)
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static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ)
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{
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return opp->src[n_IRQ].ipvp;
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}
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static inline void write_IRQreg_ide(openpic_t *opp, int n_IRQ, uint32_t val)
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{
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uint32_t tmp;
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switch (reg) {
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case IRQ_IPVP:
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/* NOTE: not fully accurate for special IRQs, but simple and
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sufficient */
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/* ACTIVITY bit is read-only */
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opp->src[n_IRQ].ipvp =
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(opp->src[n_IRQ].ipvp & 0x40000000) |
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(val & 0x800F00FF);
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openpic_update_irq(opp, n_IRQ);
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DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
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n_IRQ, val, opp->src[n_IRQ].ipvp);
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break;
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case IRQ_IDE:
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tmp = val & 0xC0000000;
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tmp |= val & ((1 << MAX_CPU) - 1);
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opp->src[n_IRQ].ide = tmp;
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DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
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break;
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}
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tmp = val & 0xC0000000;
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tmp |= val & ((1ULL << MAX_CPU) - 1);
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opp->src[n_IRQ].ide = tmp;
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DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
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}
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static inline void write_IRQreg_ipvp(openpic_t *opp, int n_IRQ, uint32_t val)
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{
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/* NOTE: not fully accurate for special IRQs, but simple and sufficient */
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/* ACTIVITY bit is read-only */
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opp->src[n_IRQ].ipvp = (opp->src[n_IRQ].ipvp & 0x40000000)
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| (val & 0x800F00FF);
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openpic_update_irq(opp, n_IRQ);
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DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
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opp->src[n_IRQ].ipvp);
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}
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#if 0 // Code provision for Intel model
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@ -516,10 +516,10 @@ static uint32_t read_doorbell_register (openpic_t *opp,
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switch (offset) {
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case DBL_IPVP_OFFSET:
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retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
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retval = read_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl);
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break;
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case DBL_IDE_OFFSET:
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retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
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retval = read_IRQreg_ide(opp, IRQ_DBL0 + n_dbl);
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break;
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case DBL_DMR_OFFSET:
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retval = opp->doorbells[n_dbl].dmr;
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@ -534,10 +534,10 @@ static void write_doorbell_register (penpic_t *opp, int n_dbl,
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{
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switch (offset) {
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case DBL_IVPR_OFFSET:
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write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
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write_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl, value);
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break;
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case DBL_IDE_OFFSET:
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write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
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write_IRQreg_ide(opp, IRQ_DBL0 + n_dbl, value);
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break;
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case DBL_DMR_OFFSET:
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opp->doorbells[n_dbl].dmr = value;
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@ -557,10 +557,10 @@ static uint32_t read_mailbox_register (openpic_t *opp,
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retval = opp->mailboxes[n_mbx].mbr;
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break;
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case MBX_IVPR_OFFSET:
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retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
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retval = read_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx);
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break;
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case MBX_DMR_OFFSET:
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retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
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retval = read_IRQreg_ide(opp, IRQ_MBX0 + n_mbx);
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break;
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}
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@ -575,10 +575,10 @@ static void write_mailbox_register (openpic_t *opp, int n_mbx,
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opp->mailboxes[n_mbx].mbr = value;
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break;
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case MBX_IVPR_OFFSET:
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write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
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write_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx, value);
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break;
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case MBX_DMR_OFFSET:
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write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
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write_IRQreg_ide(opp, IRQ_MBX0 + n_mbx, value);
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break;
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}
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}
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@ -594,18 +594,27 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
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DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
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if (addr & 0xF)
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return;
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addr &= 0xFF;
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switch (addr) {
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case 0x00: /* FREP */
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case 0x40:
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case 0x50:
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case 0x60:
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case 0x70:
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case 0x80:
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case 0x90:
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case 0xA0:
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case 0xB0:
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openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
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break;
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case 0x20: /* GLBC */
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case 0x1000: /* FREP */
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break;
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case 0x1020: /* GLBC */
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if (val & 0x80000000 && opp->reset)
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opp->reset(opp);
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opp->glbc = val & ~0x80000000;
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break;
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case 0x80: /* VENI */
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case 0x1080: /* VENI */
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break;
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case 0x90: /* PINT */
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case 0x1090: /* PINT */
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for (idx = 0; idx < opp->nb_cpus; idx++) {
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if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
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DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
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@ -619,22 +628,20 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
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}
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opp->pint = val;
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break;
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#if MAX_IPI > 0
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case 0xA0: /* IPI_IPVP */
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case 0xB0:
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case 0xC0:
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case 0xD0:
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case 0x10A0: /* IPI_IPVP */
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case 0x10B0:
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case 0x10C0:
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case 0x10D0:
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{
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int idx;
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idx = (addr - 0xA0) >> 4;
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write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP, val);
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idx = (addr - 0x10A0) >> 4;
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write_IRQreg_ipvp(opp, opp->irq_ipi0 + idx, val);
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}
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break;
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#endif
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case 0xE0: /* SPVE */
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case 0x10E0: /* SPVE */
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opp->spve = val & 0x000000FF;
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break;
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case 0xF0: /* TIFR */
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case 0x10F0: /* TIFR */
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opp->tifr = val;
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break;
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default:
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|
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@ -651,36 +658,43 @@ static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
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retval = 0xFFFFFFFF;
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if (addr & 0xF)
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return retval;
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addr &= 0xFF;
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switch (addr) {
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case 0x00: /* FREP */
|
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case 0x1000: /* FREP */
|
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retval = opp->frep;
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break;
|
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case 0x20: /* GLBC */
|
||||
case 0x1020: /* GLBC */
|
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retval = opp->glbc;
|
||||
break;
|
||||
case 0x80: /* VENI */
|
||||
case 0x1080: /* VENI */
|
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retval = opp->veni;
|
||||
break;
|
||||
case 0x90: /* PINT */
|
||||
case 0x1090: /* PINT */
|
||||
retval = 0x00000000;
|
||||
break;
|
||||
#if MAX_IPI > 0
|
||||
case 0xA0: /* IPI_IPVP */
|
||||
case 0x40:
|
||||
case 0x50:
|
||||
case 0x60:
|
||||
case 0x70:
|
||||
case 0x80:
|
||||
case 0x90:
|
||||
case 0xA0:
|
||||
case 0xB0:
|
||||
case 0xC0:
|
||||
case 0xD0:
|
||||
retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
|
||||
break;
|
||||
case 0x10A0: /* IPI_IPVP */
|
||||
case 0x10B0:
|
||||
case 0x10C0:
|
||||
case 0x10D0:
|
||||
{
|
||||
int idx;
|
||||
idx = (addr - 0xA0) >> 4;
|
||||
retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP);
|
||||
idx = (addr - 0x10A0) >> 4;
|
||||
retval = read_IRQreg_ipvp(opp, opp->irq_ipi0 + idx);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
case 0xE0: /* SPVE */
|
||||
case 0x10E0: /* SPVE */
|
||||
retval = opp->spve;
|
||||
break;
|
||||
case 0xF0: /* TIFR */
|
||||
case 0x10F0: /* TIFR */
|
||||
retval = opp->tifr;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -714,10 +728,10 @@ static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val)
|
|||
opp->timers[idx].tibc = val;
|
||||
break;
|
||||
case 0x20: /* TIVP */
|
||||
write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP, val);
|
||||
write_IRQreg_ipvp(opp, opp->irq_tim0 + idx, val);
|
||||
break;
|
||||
case 0x30: /* TIDE */
|
||||
write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE, val);
|
||||
write_IRQreg_ide(opp, opp->irq_tim0 + idx, val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -744,10 +758,10 @@ static uint32_t openpic_timer_read (void *opaque, uint32_t addr)
|
|||
retval = opp->timers[idx].tibc;
|
||||
break;
|
||||
case 0x20: /* TIPV */
|
||||
retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP);
|
||||
retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx);
|
||||
break;
|
||||
case 0x30: /* TIDE */
|
||||
retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE);
|
||||
retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx);
|
||||
break;
|
||||
}
|
||||
DPRINTF("%s: => %08x\n", __func__, retval);
|
||||
|
|
@ -767,10 +781,10 @@ static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val)
|
|||
idx = addr >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
write_IRQreg(opp, idx, IRQ_IDE, val);
|
||||
write_IRQreg_ide(opp, idx, val);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
write_IRQreg(opp, idx, IRQ_IPVP, val);
|
||||
write_IRQreg_ipvp(opp, idx, val);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -788,38 +802,40 @@ static uint32_t openpic_src_read (void *opaque, uint32_t addr)
|
|||
idx = addr >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
retval = read_IRQreg(opp, idx, IRQ_IDE);
|
||||
retval = read_IRQreg_ide(opp, idx);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
retval = read_IRQreg(opp, idx, IRQ_IPVP);
|
||||
retval = read_IRQreg_ipvp(opp, idx);
|
||||
}
|
||||
DPRINTF("%s: => %08x\n", __func__, retval);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
|
||||
uint32_t val, int idx)
|
||||
{
|
||||
openpic_t *opp = opaque;
|
||||
IRQ_src_t *src;
|
||||
IRQ_dst_t *dst;
|
||||
int idx, s_IRQ, n_IRQ;
|
||||
int s_IRQ, n_IRQ;
|
||||
|
||||
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
|
||||
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
|
||||
addr, val);
|
||||
if (addr & 0xF)
|
||||
return;
|
||||
addr &= 0x1FFF0;
|
||||
idx = addr / 0x1000;
|
||||
dst = &opp->dst[idx];
|
||||
addr &= 0xFF0;
|
||||
switch (addr) {
|
||||
#if MAX_IPI > 0
|
||||
case 0x40: /* PIPD */
|
||||
case 0x40: /* IPIDR */
|
||||
case 0x50:
|
||||
case 0x60:
|
||||
case 0x70:
|
||||
idx = (addr - 0x40) >> 4;
|
||||
write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE, val);
|
||||
/* we use IDE as mask which CPUs to deliver the IPI to still. */
|
||||
write_IRQreg_ide(opp, opp->irq_ipi0 + idx,
|
||||
opp->src[opp->irq_ipi0 + idx].ide | val);
|
||||
openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
|
||||
openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
|
||||
break;
|
||||
|
|
@ -856,20 +872,24 @@ static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t v
|
|||
}
|
||||
}
|
||||
|
||||
static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
|
||||
static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
|
||||
}
|
||||
|
||||
static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
|
||||
int idx)
|
||||
{
|
||||
openpic_t *opp = opaque;
|
||||
IRQ_src_t *src;
|
||||
IRQ_dst_t *dst;
|
||||
uint32_t retval;
|
||||
int idx, n_IRQ;
|
||||
int n_IRQ;
|
||||
|
||||
DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
|
||||
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr);
|
||||
retval = 0xFFFFFFFF;
|
||||
if (addr & 0xF)
|
||||
return retval;
|
||||
addr &= 0x1FFF0;
|
||||
idx = addr / 0x1000;
|
||||
dst = &opp->dst[idx];
|
||||
addr &= 0xFF0;
|
||||
switch (addr) {
|
||||
|
|
@ -909,18 +929,22 @@ static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
|
|||
reset_bit(&src->ipvp, IPVP_ACTIVITY);
|
||||
src->pending = 0;
|
||||
}
|
||||
|
||||
if ((n_IRQ >= opp->irq_ipi0) && (n_IRQ < (opp->irq_ipi0 + MAX_IPI))) {
|
||||
src->ide &= ~(1 << idx);
|
||||
if (src->ide && !test_bit(&src->ipvp, IPVP_SENSE)) {
|
||||
/* trigger on CPUs that didn't know about it yet */
|
||||
openpic_set_irq(opp, n_IRQ, 1);
|
||||
openpic_set_irq(opp, n_IRQ, 0);
|
||||
/* if all CPUs knew about it, set active bit again */
|
||||
set_bit(&src->ipvp, IPVP_ACTIVITY);
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0xB0: /* PEOI */
|
||||
retval = 0;
|
||||
break;
|
||||
#if MAX_IPI > 0
|
||||
case 0x40: /* IDE */
|
||||
case 0x50:
|
||||
idx = (addr - 0x40) >> 4;
|
||||
retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -929,6 +953,11 @@ static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
|
|||
return retval;
|
||||
}
|
||||
|
||||
static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
|
||||
{
|
||||
return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
|
||||
}
|
||||
|
||||
static void openpic_buggy_write (void *opaque,
|
||||
target_phys_addr_t addr, uint32_t val)
|
||||
{
|
||||
|
|
@ -1247,7 +1276,7 @@ static void mpic_reset (void *opaque)
|
|||
|
||||
mpp->glbc = 0x80000000;
|
||||
/* Initialise controller registers */
|
||||
mpp->frep = 0x004f0002;
|
||||
mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8);
|
||||
mpp->veni = VENI;
|
||||
mpp->pint = 0x00000000;
|
||||
mpp->spve = 0x0000FFFF;
|
||||
|
|
@ -1256,6 +1285,10 @@ static void mpic_reset (void *opaque)
|
|||
mpp->src[i].ipvp = 0x80800000;
|
||||
mpp->src[i].ide = 0x00000001;
|
||||
}
|
||||
/* Set IDE for IPIs to 0 so we don't get spurious interrupts */
|
||||
for (i = mpp->irq_ipi0; i < (mpp->irq_ipi0 + MAX_IPI); i++) {
|
||||
mpp->src[i].ide = 0;
|
||||
}
|
||||
/* Initialise IRQ destinations */
|
||||
for (i = 0; i < MAX_CPU; i++) {
|
||||
mpp->dst[i].pctp = 0x0000000F;
|
||||
|
|
@ -1296,13 +1329,13 @@ static void mpic_timer_write (void *opaque, target_phys_addr_t addr, uint32_t va
|
|||
mpp->timers[idx].tibc = val;
|
||||
break;
|
||||
case 0x20: /* GTIVPR */
|
||||
write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP, val);
|
||||
write_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx, val);
|
||||
break;
|
||||
case 0x30: /* GTIDR & TFRR */
|
||||
if ((addr & 0xF0) == 0xF0)
|
||||
mpp->dst[cpu].tfrr = val;
|
||||
else
|
||||
write_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE, val);
|
||||
write_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx, val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1328,13 +1361,13 @@ static uint32_t mpic_timer_read (void *opaque, target_phys_addr_t addr)
|
|||
retval = mpp->timers[idx].tibc;
|
||||
break;
|
||||
case 0x20: /* TIPV */
|
||||
retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP);
|
||||
retval = read_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx);
|
||||
break;
|
||||
case 0x30: /* TIDR */
|
||||
if ((addr &0xF0) == 0XF0)
|
||||
retval = mpp->dst[cpu].tfrr;
|
||||
else
|
||||
retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE);
|
||||
retval = read_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx);
|
||||
break;
|
||||
}
|
||||
DPRINTF("%s: => %08x\n", __func__, retval);
|
||||
|
|
@ -1357,10 +1390,10 @@ static void mpic_src_ext_write (void *opaque, target_phys_addr_t addr,
|
|||
idx += (addr & 0xFFF0) >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
write_IRQreg(mpp, idx, IRQ_IDE, val);
|
||||
write_IRQreg_ide(mpp, idx, val);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
write_IRQreg(mpp, idx, IRQ_IPVP, val);
|
||||
write_IRQreg_ipvp(mpp, idx, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1381,10 +1414,10 @@ static uint32_t mpic_src_ext_read (void *opaque, target_phys_addr_t addr)
|
|||
idx += (addr & 0xFFF0) >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
retval = read_IRQreg(mpp, idx, IRQ_IDE);
|
||||
retval = read_IRQreg_ide(mpp, idx);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
retval = read_IRQreg(mpp, idx, IRQ_IPVP);
|
||||
retval = read_IRQreg_ipvp(mpp, idx);
|
||||
}
|
||||
DPRINTF("%s: => %08x\n", __func__, retval);
|
||||
}
|
||||
|
|
@ -1407,10 +1440,10 @@ static void mpic_src_int_write (void *opaque, target_phys_addr_t addr,
|
|||
idx += (addr & 0xFFF0) >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
write_IRQreg(mpp, idx, IRQ_IDE, val);
|
||||
write_IRQreg_ide(mpp, idx, val);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
write_IRQreg(mpp, idx, IRQ_IPVP, val);
|
||||
write_IRQreg_ipvp(mpp, idx, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1431,10 +1464,10 @@ static uint32_t mpic_src_int_read (void *opaque, target_phys_addr_t addr)
|
|||
idx += (addr & 0xFFF0) >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
retval = read_IRQreg(mpp, idx, IRQ_IDE);
|
||||
retval = read_IRQreg_ide(mpp, idx);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
retval = read_IRQreg(mpp, idx, IRQ_IPVP);
|
||||
retval = read_IRQreg_ipvp(mpp, idx);
|
||||
}
|
||||
DPRINTF("%s: => %08x\n", __func__, retval);
|
||||
}
|
||||
|
|
@ -1457,10 +1490,10 @@ static void mpic_src_msg_write (void *opaque, target_phys_addr_t addr,
|
|||
idx += (addr & 0xFFF0) >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
write_IRQreg(mpp, idx, IRQ_IDE, val);
|
||||
write_IRQreg_ide(mpp, idx, val);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
write_IRQreg(mpp, idx, IRQ_IPVP, val);
|
||||
write_IRQreg_ipvp(mpp, idx, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1481,10 +1514,10 @@ static uint32_t mpic_src_msg_read (void *opaque, target_phys_addr_t addr)
|
|||
idx += (addr & 0xFFF0) >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
retval = read_IRQreg(mpp, idx, IRQ_IDE);
|
||||
retval = read_IRQreg_ide(mpp, idx);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
retval = read_IRQreg(mpp, idx, IRQ_IPVP);
|
||||
retval = read_IRQreg_ipvp(mpp, idx);
|
||||
}
|
||||
DPRINTF("%s: => %08x\n", __func__, retval);
|
||||
}
|
||||
|
|
@ -1507,10 +1540,10 @@ static void mpic_src_msi_write (void *opaque, target_phys_addr_t addr,
|
|||
idx += (addr & 0xFFF0) >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
write_IRQreg(mpp, idx, IRQ_IDE, val);
|
||||
write_IRQreg_ide(mpp, idx, val);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
write_IRQreg(mpp, idx, IRQ_IPVP, val);
|
||||
write_IRQreg_ipvp(mpp, idx, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1530,10 +1563,10 @@ static uint32_t mpic_src_msi_read (void *opaque, target_phys_addr_t addr)
|
|||
idx += (addr & 0xFFF0) >> 5;
|
||||
if (addr & 0x10) {
|
||||
/* EXDE / IFEDE / IEEDE */
|
||||
retval = read_IRQreg(mpp, idx, IRQ_IDE);
|
||||
retval = read_IRQreg_ide(mpp, idx);
|
||||
} else {
|
||||
/* EXVP / IFEVP / IEEVP */
|
||||
retval = read_IRQreg(mpp, idx, IRQ_IPVP);
|
||||
retval = read_IRQreg_ipvp(mpp, idx);
|
||||
}
|
||||
DPRINTF("%s: => %08x\n", __func__, retval);
|
||||
}
|
||||
|
|
@ -1659,10 +1692,6 @@ qemu_irq *mpic_init (MemoryRegion *address_space, target_phys_addr_t base,
|
|||
{"cpu", &mpic_cpu_ops, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
|
||||
};
|
||||
|
||||
/* XXX: for now, only one CPU is supported */
|
||||
if (nb_cpus != 1)
|
||||
return NULL;
|
||||
|
||||
mpp = g_malloc0(sizeof(openpic_t));
|
||||
|
||||
memory_region_init(&mpp->mem, "mpic", 0x40000);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue