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* whpx fixes in preparation for GDB support (Ivan)
* VSS header fixes (Marc-André) * 5-level EPT support (Vitaly) * AMX support (Jing Liu & Yang Zhong) * Bundle changes to MSI routes (Longpeng) * More precise emulation of #SS (Gareth) * Disable ASAN testing -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmIwb5QUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroOOUQf8DiNcq8XVVMdX946Qwa4pSxc4ZJtF X+RkNsscluuLJ2vGEFKwPVps6c6UPqAhXUruZOQmcLmma511MsyJrxyfd4iRgPD2 tL1+n4RpfsbnTEGT8c6TFWWMEIOjLTbKmR/SIxuxpeVG3xlk6tlCevykrIdc90gP vQIByTGFx3GwiPyDo0j92mA/CsWLnfq6zQ2Tox1xCyt8R+QDimqG0KGLc5RAyiyC ZmilN2yaqizDfkIzinwHG6gP1NGwVUsrUNl4X9C4mwEMFnsXiyKP5n/BlDZ7w4Wb QXalFpPg1hJxRGGvyta6OF9VmCfmK9Q0FNVWm1lPE5adn3ECHFo6FJKvfg== =LVgf -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * whpx fixes in preparation for GDB support (Ivan) * VSS header fixes (Marc-André) * 5-level EPT support (Vitaly) * AMX support (Jing Liu & Yang Zhong) * Bundle changes to MSI routes (Longpeng) * More precise emulation of #SS (Gareth) * Disable ASAN testing # gpg: Signature made Tue 15 Mar 2022 10:51:00 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (22 commits) gitlab-ci: do not run tests with address sanitizer KVM: SVM: always set MSR_AMD64_TSC_RATIO to default value i386: Add Icelake-Server-v6 CPU model with 5-level EPT support x86: Support XFD and AMX xsave data migration x86: add support for KVM_CAP_XSAVE2 and AMX state migration x86: Add AMX CPUIDs enumeration x86: Add XFD faulting bit for state components x86: Grant AMX permission for guest x86: Add AMX XTILECFG and XTILEDATA components x86: Fix the 64-byte boundary enumeration for extended state linux-headers: include missing changes from 5.17 target/i386: Throw a #SS when loading a non-canonical IST target/i386: only include bits in pg_mode if they are not ignored kvm/msi: do explicit commit when adding msi routes kvm-irqchip: introduce new API to support route change update meson-buildoptions.sh qga/vss: update informative message about MinGW qga/vss-win32: check old VSS SDK headers meson: fix generic location of vss headers vmxcap: Add 5-level EPT bit ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
dee3a86d54
26 changed files with 451 additions and 85 deletions
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@ -424,16 +424,19 @@ static void ivshmem_add_kvm_msi_virq(IVShmemState *s, int vector,
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Error **errp)
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{
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PCIDevice *pdev = PCI_DEVICE(s);
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KVMRouteChange c;
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int ret;
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IVSHMEM_DPRINTF("ivshmem_add_kvm_msi_virq vector:%d\n", vector);
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assert(!s->msi_vectors[vector].pdev);
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ret = kvm_irqchip_add_msi_route(kvm_state, vector, pdev);
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c = kvm_irqchip_begin_route_changes(kvm_state);
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ret = kvm_irqchip_add_msi_route(&c, vector, pdev);
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if (ret < 0) {
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error_setg(errp, "kvm_irqchip_add_msi_route failed");
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return;
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}
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kvm_irqchip_commit_route_changes(&c);
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s->msi_vectors[vector].virq = ret;
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s->msi_vectors[vector].pdev = pdev;
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@ -412,6 +412,7 @@ static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix)
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static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector,
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int vector_n, bool msix)
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{
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KVMRouteChange c;
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int virq;
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if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) {
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@ -422,11 +423,13 @@ static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector,
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return;
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}
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virq = kvm_irqchip_add_msi_route(kvm_state, vector_n, &vdev->pdev);
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c = kvm_irqchip_begin_route_changes(kvm_state);
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virq = kvm_irqchip_add_msi_route(&c, vector_n, &vdev->pdev);
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if (virq < 0) {
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event_notifier_cleanup(&vector->kvm_interrupt);
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return;
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}
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kvm_irqchip_commit_route_changes(&c);
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if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt,
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NULL, virq) < 0) {
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@ -683,10 +683,12 @@ static int kvm_virtio_pci_vq_vector_use(VirtIOPCIProxy *proxy,
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int ret;
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if (irqfd->users == 0) {
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ret = kvm_irqchip_add_msi_route(kvm_state, vector, &proxy->pci_dev);
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KVMRouteChange c = kvm_irqchip_begin_route_changes(kvm_state);
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ret = kvm_irqchip_add_msi_route(&c, vector, &proxy->pci_dev);
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if (ret < 0) {
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return ret;
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}
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kvm_irqchip_commit_route_changes(&c);
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irqfd->virq = ret;
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}
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irqfd->users++;
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