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ppc patch queue 2020-08-18
Here's my first pull request for qemu-5.2, which has quite a few accumulated things. Highlights are: * Preliminary support for POWER10 (Power ISA 3.1) instruction emulation * Add documentation on the (very confusing) pseries NUMA configuration * Fix some bugs handling edge cases with XICS, XIVE and kernel_irqchip * Fix icount for a number of POWER registers * Many cleanups to error handling in XIVE code * Validate size of -prom-env data -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAl87VpwACgkQbDjKyiDZ s5LjIxAAs8YAQe3uDRz1Wb9GftoMmEHdq7JQoO0FbXDQIVXzpTAXmFLSBtCWKl6p O1MEIy/o48b5ORXJqSDSA5LgxbHxYfHdIPEY5Tbn/TGvTvKyCukx9n11milUG8In JxRrOTQBnQAAHkLoyuZyrWKOauC0N1scNrnX9Geuid13GcmqHg1d2alXAUu8jEeC HSiVmtMqqyyqTx2xA4vfhaGuuwTthnKNfbGdg9ksVqBsCW+etn6ZKGImt8hBe3qO 5iqbQZvFbkpzgbjkhDzUDM6tmUAFN55y/Y+y7I8Tz4/IX7d3WbdqpplwrXXVWkpq 2gcBBjQ/9a1hPTBRVN9jn4CvHfhILBfeHIElUiLpSTQZQQALymTnnI2pLCgKoEFX LcchXbjiX+pZ2OJnAijpwBcknjgT2U/ZNyiqHJfSQ6jzlYx1YtUf4xGUsgloSiK8 9QDK8o2k0Cm8Be+lPMBMmTctoi8bq+8SN5UUF710WQL235J58o9+z1vuGO2HVk3x flBtv/+B890wcCDpGU80DPs/LSzR0xTTbA5JsWft2fvO569mda0MoWkJH5w6jvSc ZLYqljCzFCVW+tKiGHzaBalJaMwn0+QMDTsxzP3yTt5LmmEeRXpBELgvrW64IobD xBeryH3nG4SwxFSJq+4ATfvUzjy/Eo58lTTl6c53Ji8/D3aFwsA= =L9Wi -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200818' into staging ppc patch queue 2020-08-18 Here's my first pull request for qemu-5.2, which has quite a few accumulated things. Highlights are: * Preliminary support for POWER10 (Power ISA 3.1) instruction emulation * Add documentation on the (very confusing) pseries NUMA configuration * Fix some bugs handling edge cases with XICS, XIVE and kernel_irqchip * Fix icount for a number of POWER registers * Many cleanups to error handling in XIVE code * Validate size of -prom-env data # gpg: Signature made Tue 18 Aug 2020 05:18:36 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.2-20200818: (40 commits) spapr/xive: Use xive_source_esb_len() nvram: Exit QEMU if NVRAM cannot contain all -prom-env data spapr/xive: Simplify error handling of kvmppc_xive_cpu_synchronize_state() ppc/xive: Simplify error handling in xive_tctx_realize() spapr/xive: Simplify error handling in kvmppc_xive_connect() ppc/xive: Fix error handling in vmstate_xive_tctx_*() callbacks spapr/xive: Fix error handling in kvmppc_xive_post_load() spapr/kvm: Fix error handling in kvmppc_xive_pre_save() spapr/xive: Rework error handling of kvmppc_xive_set_source_config() spapr/xive: Rework error handling in kvmppc_xive_get_queues() spapr/xive: Rework error handling of kvmppc_xive_[gs]et_queue_config() spapr/xive: Rework error handling of kvmppc_xive_cpu_[gs]et_state() spapr/xive: Rework error handling of kvmppc_xive_mmap() spapr/xive: Rework error handling of kvmppc_xive_source_reset() spapr/xive: Rework error handling of kvmppc_xive_cpu_connect() spapr: Simplify error handling in spapr_phb_realize() spapr/xive: Convert KVM device fd checks to assert() ppc/xive: Introduce dedicated kvm_irqchip_in_kernel() wrappers ppc/xive: Rework setup of XiveSource::esb_mmio target/ppc: Integrate icount to purr, vtb, and tbu40 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
dd8014e4e9
29 changed files with 719 additions and 302 deletions
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@ -2191,6 +2191,8 @@ enum {
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PPC2_PM_ISA206 = 0x0000000000040000ULL,
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/* POWER ISA 3.0 */
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PPC2_ISA300 = 0x0000000000080000ULL,
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/* POWER ISA 3.1 */
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PPC2_ISA310 = 0x0000000000100000ULL,
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#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
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PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
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@ -2199,7 +2201,7 @@ enum {
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PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
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PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
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PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
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PPC2_ISA300)
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PPC2_ISA300 | PPC2_ISA310)
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};
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/*****************************************************************************/
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@ -184,7 +184,10 @@ DEF_HELPER_3(vmulosw, void, avr, avr, avr)
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DEF_HELPER_3(vmuloub, void, avr, avr, avr)
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DEF_HELPER_3(vmulouh, void, avr, avr, avr)
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DEF_HELPER_3(vmulouw, void, avr, avr, avr)
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DEF_HELPER_3(vmuluwm, void, avr, avr, avr)
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DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
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DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
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DEF_HELPER_3(vmulhsd, void, avr, avr, avr)
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DEF_HELPER_3(vmulhud, void, avr, avr, avr)
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DEF_HELPER_3(vslo, void, avr, avr, avr)
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DEF_HELPER_3(vsro, void, avr, avr, avr)
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DEF_HELPER_3(vsrv, void, avr, avr, avr)
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@ -523,19 +523,6 @@ void helper_vprtybq(ppc_avr_t *r, ppc_avr_t *b)
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r->VsrD(0) = 0;
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}
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#define VARITH_DO(name, op, element) \
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void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
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{ \
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int i; \
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\
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for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
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r->element[i] = a->element[i] op b->element[i]; \
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} \
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}
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VARITH_DO(muluwm, *, u32)
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#undef VARITH_DO
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#undef VARITH
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#define VARITHFP(suffix, func) \
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void helper_v##suffix(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, \
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ppc_avr_t *b) \
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@ -1099,6 +1086,41 @@ VMUL(uw, u32, VsrW, VsrD, uint64_t)
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#undef VMUL_DO_ODD
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#undef VMUL
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void helper_vmulhsw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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{
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int i;
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for (i = 0; i < 4; i++) {
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r->s32[i] = (int32_t)(((int64_t)a->s32[i] * (int64_t)b->s32[i]) >> 32);
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}
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}
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void helper_vmulhuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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{
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int i;
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for (i = 0; i < 4; i++) {
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r->u32[i] = (uint32_t)(((uint64_t)a->u32[i] *
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(uint64_t)b->u32[i]) >> 32);
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}
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}
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void helper_vmulhsd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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{
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uint64_t discard;
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muls64(&discard, &r->u64[0], a->s64[0], b->s64[0]);
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muls64(&discard, &r->u64[1], a->s64[1], b->s64[1]);
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}
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void helper_vmulhud(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
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{
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uint64_t discard;
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mulu64(&discard, &r->u64[0], a->u64[0], b->u64[0]);
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mulu64(&discard, &r->u64[1], a->u64[1], b->u64[1]);
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}
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void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
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ppc_avr_t *c)
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{
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@ -6971,7 +6971,47 @@ static void gen_dform3D(DisasContext *ctx)
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return gen_invalid(ctx);
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}
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#if defined(TARGET_PPC64)
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/* brd */
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static void gen_brd(DisasContext *ctx)
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{
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tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
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}
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/* brw */
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static void gen_brw(DisasContext *ctx)
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{
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tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
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tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
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}
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/* brh */
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static void gen_brh(DisasContext *ctx)
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{
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TCGv_i64 t0 = tcg_temp_new_i64();
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 t2 = tcg_temp_new_i64();
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tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
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tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
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tcg_gen_and_i64(t2, t1, t0);
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tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
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tcg_gen_shli_i64(t1, t1, 8);
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tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(t2);
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}
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#endif
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static opcode_t opcodes[] = {
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#if defined(TARGET_PPC64)
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GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
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GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
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GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
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#endif
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GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
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GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
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GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
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@ -349,14 +349,24 @@ static inline void gen_evmergelohi(DisasContext *ctx)
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}
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static inline void gen_evsplati(DisasContext *ctx)
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{
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uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
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uint64_t imm;
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
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tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
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tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
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}
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static inline void gen_evsplatfi(DisasContext *ctx)
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{
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uint64_t imm = rA(ctx->opcode) << 27;
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uint64_t imm;
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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imm = rA(ctx->opcode) << 27;
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tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
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tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
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@ -389,21 +399,37 @@ static inline void gen_evsel(DisasContext *ctx)
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static void gen_evsel0(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evsel(ctx);
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}
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static void gen_evsel1(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evsel(ctx);
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}
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static void gen_evsel2(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evsel(ctx);
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}
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static void gen_evsel3(DisasContext *ctx)
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{
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evsel(ctx);
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}
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@ -518,6 +544,11 @@ static inline void gen_evmwsmia(DisasContext *ctx)
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{
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TCGv_i64 tmp;
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evmwsmi(ctx); /* rD := rA * rB */
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tmp = tcg_temp_new_i64();
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@ -531,8 +562,13 @@ static inline void gen_evmwsmia(DisasContext *ctx)
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static inline void gen_evmwsmiaa(DisasContext *ctx)
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{
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TCGv_i64 acc = tcg_temp_new_i64();
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TCGv_i64 tmp = tcg_temp_new_i64();
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TCGv_i64 acc;
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TCGv_i64 tmp;
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if (unlikely(!ctx->spe_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_SPEU);
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return;
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}
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gen_evmwsmi(ctx); /* rD := rA * rB */
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@ -892,8 +928,14 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_CONV_32_64(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i64 t0 = tcg_temp_new_i64(); \
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TCGv_i32 t1 = tcg_temp_new_i32(); \
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TCGv_i64 t0; \
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TCGv_i32 t1; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i64(); \
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t1 = tcg_temp_new_i32(); \
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gen_load_gpr64(t0, rB(ctx->opcode)); \
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gen_helper_##name(t1, cpu_env, t0); \
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tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
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@ -903,8 +945,14 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_CONV_64_32(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i64 t0 = tcg_temp_new_i64(); \
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TCGv_i32 t1 = tcg_temp_new_i32(); \
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TCGv_i64 t0; \
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TCGv_i32 t1; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i64(); \
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t1 = tcg_temp_new_i32(); \
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
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gen_helper_##name(t0, cpu_env, t1); \
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gen_store_gpr64(rD(ctx->opcode), t0); \
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@ -914,7 +962,12 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_CONV_64_64(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i64 t0 = tcg_temp_new_i64(); \
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TCGv_i64 t0; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i64(); \
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gen_load_gpr64(t0, rB(ctx->opcode)); \
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gen_helper_##name(t0, cpu_env, t0); \
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gen_store_gpr64(rD(ctx->opcode), t0); \
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@ -923,13 +976,8 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_ARITH2_32_32(name) \
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static inline void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i32 t0, t1; \
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if (unlikely(!ctx->spe_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_SPEU); \
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return; \
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} \
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t0 = tcg_temp_new_i32(); \
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t1 = tcg_temp_new_i32(); \
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TCGv_i32 t0 = tcg_temp_new_i32(); \
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TCGv_i32 t1 = tcg_temp_new_i32(); \
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tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
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tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
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gen_helper_##name(t0, cpu_env, t0, t1); \
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@ -958,13 +1006,8 @@ static inline void gen_##name(DisasContext *ctx) \
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#define GEN_SPEFPUOP_COMP_32(name) \
|
||||
static inline void gen_##name(DisasContext *ctx) \
|
||||
{ \
|
||||
TCGv_i32 t0, t1; \
|
||||
if (unlikely(!ctx->spe_enabled)) { \
|
||||
gen_exception(ctx, POWERPC_EXCP_SPEU); \
|
||||
return; \
|
||||
} \
|
||||
t0 = tcg_temp_new_i32(); \
|
||||
t1 = tcg_temp_new_i32(); \
|
||||
TCGv_i32 t0 = tcg_temp_new_i32(); \
|
||||
TCGv_i32 t1 = tcg_temp_new_i32(); \
|
||||
\
|
||||
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
|
||||
tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
|
||||
|
|
@ -1074,28 +1117,16 @@ GEN_SPEFPUOP_ARITH2_32_32(efsmul);
|
|||
GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
|
||||
static inline void gen_efsabs(DisasContext *ctx)
|
||||
{
|
||||
if (unlikely(!ctx->spe_enabled)) {
|
||||
gen_exception(ctx, POWERPC_EXCP_SPEU);
|
||||
return;
|
||||
}
|
||||
tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
|
||||
(target_long)~0x80000000LL);
|
||||
}
|
||||
static inline void gen_efsnabs(DisasContext *ctx)
|
||||
{
|
||||
if (unlikely(!ctx->spe_enabled)) {
|
||||
gen_exception(ctx, POWERPC_EXCP_SPEU);
|
||||
return;
|
||||
}
|
||||
tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
|
||||
0x80000000);
|
||||
}
|
||||
static inline void gen_efsneg(DisasContext *ctx)
|
||||
{
|
||||
if (unlikely(!ctx->spe_enabled)) {
|
||||
gen_exception(ctx, POWERPC_EXCP_SPEU);
|
||||
return;
|
||||
}
|
||||
tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
|
||||
0x80000000);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -801,18 +801,27 @@ static void trans_vclzd(DisasContext *ctx)
|
|||
GEN_VXFORM(vmuloub, 4, 0);
|
||||
GEN_VXFORM(vmulouh, 4, 1);
|
||||
GEN_VXFORM(vmulouw, 4, 2);
|
||||
GEN_VXFORM(vmuluwm, 4, 2);
|
||||
GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
|
||||
GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
|
||||
vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
|
||||
GEN_VXFORM(vmulosb, 4, 4);
|
||||
GEN_VXFORM(vmulosh, 4, 5);
|
||||
GEN_VXFORM(vmulosw, 4, 6);
|
||||
GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
|
||||
GEN_VXFORM(vmuleub, 4, 8);
|
||||
GEN_VXFORM(vmuleuh, 4, 9);
|
||||
GEN_VXFORM(vmuleuw, 4, 10);
|
||||
GEN_VXFORM(vmulhuw, 4, 10);
|
||||
GEN_VXFORM(vmulhud, 4, 11);
|
||||
GEN_VXFORM_DUAL(vmuleuw, PPC_ALTIVEC, PPC_NONE,
|
||||
vmulhuw, PPC_NONE, PPC2_ISA310);
|
||||
GEN_VXFORM(vmulesb, 4, 12);
|
||||
GEN_VXFORM(vmulesh, 4, 13);
|
||||
GEN_VXFORM(vmulesw, 4, 14);
|
||||
GEN_VXFORM(vmulhsw, 4, 14);
|
||||
GEN_VXFORM_DUAL(vmulesw, PPC_ALTIVEC, PPC_NONE,
|
||||
vmulhsw, PPC_NONE, PPC2_ISA310);
|
||||
GEN_VXFORM(vmulhsd, 4, 15);
|
||||
GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
|
||||
GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
|
||||
GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
|
||||
|
|
|
|||
|
|
@ -48,6 +48,9 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
|
|||
GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
|
||||
PPC2_ISA300)
|
||||
|
||||
#define GEN_VXFORM_310(name, opc2, opc3) \
|
||||
GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
|
||||
|
||||
#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
|
||||
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
|
||||
|
||||
|
|
@ -104,12 +107,15 @@ GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
|
|||
GEN_VXFORM(vmulosb, 4, 4),
|
||||
GEN_VXFORM(vmulosh, 4, 5),
|
||||
GEN_VXFORM_207(vmulosw, 4, 6),
|
||||
GEN_VXFORM_310(vmulld, 4, 7),
|
||||
GEN_VXFORM(vmuleub, 4, 8),
|
||||
GEN_VXFORM(vmuleuh, 4, 9),
|
||||
GEN_VXFORM_207(vmuleuw, 4, 10),
|
||||
GEN_VXFORM_DUAL(vmuleuw, vmulhuw, 4, 10, PPC_ALTIVEC, PPC_NONE),
|
||||
GEN_VXFORM_310(vmulhud, 4, 11),
|
||||
GEN_VXFORM(vmulesb, 4, 12),
|
||||
GEN_VXFORM(vmulesh, 4, 13),
|
||||
GEN_VXFORM_207(vmulesw, 4, 14),
|
||||
GEN_VXFORM_DUAL(vmulesw, vmulhsw, 4, 14, PPC_ALTIVEC, PPC_NONE),
|
||||
GEN_VXFORM_310(vmulhsd, 4, 15),
|
||||
GEN_VXFORM(vslb, 2, 4),
|
||||
GEN_VXFORM(vslh, 2, 5),
|
||||
GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
|
||||
|
|
|
|||
|
|
@ -284,12 +284,24 @@ static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
|
|||
ATTRIBUTE_UNUSED
|
||||
static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_stop_exception(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_stop_exception(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
/* HDECR */
|
||||
|
|
@ -319,17 +331,35 @@ static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
|
|||
|
||||
static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
|
||||
{
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_stop_exception(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_stop_exception(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
|
||||
{
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_io_start();
|
||||
}
|
||||
gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
|
||||
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
|
||||
gen_stop_exception(ctx);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -9201,7 +9231,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
|
|||
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
|
||||
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
|
||||
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
|
||||
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
|
||||
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
|
||||
pcc->msr_mask = (1ull << MSR_SF) |
|
||||
(1ull << MSR_HV) |
|
||||
(1ull << MSR_TM) |
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue