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https://github.com/Motorhead1991/qemu.git
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ppc patch queue 2020-08-18
Here's my first pull request for qemu-5.2, which has quite a few accumulated things. Highlights are: * Preliminary support for POWER10 (Power ISA 3.1) instruction emulation * Add documentation on the (very confusing) pseries NUMA configuration * Fix some bugs handling edge cases with XICS, XIVE and kernel_irqchip * Fix icount for a number of POWER registers * Many cleanups to error handling in XIVE code * Validate size of -prom-env data -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAl87VpwACgkQbDjKyiDZ s5LjIxAAs8YAQe3uDRz1Wb9GftoMmEHdq7JQoO0FbXDQIVXzpTAXmFLSBtCWKl6p O1MEIy/o48b5ORXJqSDSA5LgxbHxYfHdIPEY5Tbn/TGvTvKyCukx9n11milUG8In JxRrOTQBnQAAHkLoyuZyrWKOauC0N1scNrnX9Geuid13GcmqHg1d2alXAUu8jEeC HSiVmtMqqyyqTx2xA4vfhaGuuwTthnKNfbGdg9ksVqBsCW+etn6ZKGImt8hBe3qO 5iqbQZvFbkpzgbjkhDzUDM6tmUAFN55y/Y+y7I8Tz4/IX7d3WbdqpplwrXXVWkpq 2gcBBjQ/9a1hPTBRVN9jn4CvHfhILBfeHIElUiLpSTQZQQALymTnnI2pLCgKoEFX LcchXbjiX+pZ2OJnAijpwBcknjgT2U/ZNyiqHJfSQ6jzlYx1YtUf4xGUsgloSiK8 9QDK8o2k0Cm8Be+lPMBMmTctoi8bq+8SN5UUF710WQL235J58o9+z1vuGO2HVk3x flBtv/+B890wcCDpGU80DPs/LSzR0xTTbA5JsWft2fvO569mda0MoWkJH5w6jvSc ZLYqljCzFCVW+tKiGHzaBalJaMwn0+QMDTsxzP3yTt5LmmEeRXpBELgvrW64IobD xBeryH3nG4SwxFSJq+4ATfvUzjy/Eo58lTTl6c53Ji8/D3aFwsA= =L9Wi -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200818' into staging ppc patch queue 2020-08-18 Here's my first pull request for qemu-5.2, which has quite a few accumulated things. Highlights are: * Preliminary support for POWER10 (Power ISA 3.1) instruction emulation * Add documentation on the (very confusing) pseries NUMA configuration * Fix some bugs handling edge cases with XICS, XIVE and kernel_irqchip * Fix icount for a number of POWER registers * Many cleanups to error handling in XIVE code * Validate size of -prom-env data # gpg: Signature made Tue 18 Aug 2020 05:18:36 BST # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.2-20200818: (40 commits) spapr/xive: Use xive_source_esb_len() nvram: Exit QEMU if NVRAM cannot contain all -prom-env data spapr/xive: Simplify error handling of kvmppc_xive_cpu_synchronize_state() ppc/xive: Simplify error handling in xive_tctx_realize() spapr/xive: Simplify error handling in kvmppc_xive_connect() ppc/xive: Fix error handling in vmstate_xive_tctx_*() callbacks spapr/xive: Fix error handling in kvmppc_xive_post_load() spapr/kvm: Fix error handling in kvmppc_xive_pre_save() spapr/xive: Rework error handling of kvmppc_xive_set_source_config() spapr/xive: Rework error handling in kvmppc_xive_get_queues() spapr/xive: Rework error handling of kvmppc_xive_[gs]et_queue_config() spapr/xive: Rework error handling of kvmppc_xive_cpu_[gs]et_state() spapr/xive: Rework error handling of kvmppc_xive_mmap() spapr/xive: Rework error handling of kvmppc_xive_source_reset() spapr/xive: Rework error handling of kvmppc_xive_cpu_connect() spapr: Simplify error handling in spapr_phb_realize() spapr/xive: Convert KVM device fd checks to assert() ppc/xive: Introduce dedicated kvm_irqchip_in_kernel() wrappers ppc/xive: Rework setup of XiveSource::esb_mmio target/ppc: Integrate icount to purr, vtb, and tbu40 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
dd8014e4e9
29 changed files with 719 additions and 302 deletions
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@ -558,7 +558,8 @@ static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr,
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int nb_numa_nodes = machine->numa_state->num_nodes;
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int ret, i, offset;
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uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
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uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
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uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32),
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cpu_to_be32(lmb_size & 0xffffffff)};
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uint32_t *int_buf, *cur_index, buf_len;
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int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
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MemoryDeviceInfoList *dimms = NULL;
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@ -905,7 +906,8 @@ static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
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uint32_t lrdr_capacity[] = {
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cpu_to_be32(max_device_addr >> 32),
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cpu_to_be32(max_device_addr & 0xffffffff),
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0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
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cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32),
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cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff),
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cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
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};
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uint32_t maxdomain = cpu_to_be32(spapr->gpu_numa_id > 1 ? 1 : 0);
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@ -180,24 +180,24 @@ static void spapr_cap_set_pagesize(Object *obj, Visitor *v, const char *name,
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static void cap_htm_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
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{
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ERRP_GUARD();
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if (!val) {
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/* TODO: We don't support disabling htm yet */
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return;
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}
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if (tcg_enabled()) {
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error_setg(errp,
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"No Transactional Memory support in TCG,"
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" try appending -machine cap-htm=off");
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error_setg(errp, "No Transactional Memory support in TCG");
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error_append_hint(errp, "Try appending -machine cap-htm=off\n");
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} else if (kvm_enabled() && !kvmppc_has_cap_htm()) {
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error_setg(errp,
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"KVM implementation does not support Transactional Memory,"
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" try appending -machine cap-htm=off"
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);
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"KVM implementation does not support Transactional Memory");
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error_append_hint(errp, "Try appending -machine cap-htm=off\n");
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}
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}
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static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
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{
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ERRP_GUARD();
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PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
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CPUPPCState *env = &cpu->env;
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@ -209,13 +209,14 @@ static void cap_vsx_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
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* rid of anything that doesn't do VMX */
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g_assert(env->insns_flags & PPC_ALTIVEC);
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if (!(env->insns_flags2 & PPC2_VSX)) {
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error_setg(errp, "VSX support not available,"
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" try appending -machine cap-vsx=off");
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error_setg(errp, "VSX support not available");
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error_append_hint(errp, "Try appending -machine cap-vsx=off\n");
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}
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}
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static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
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{
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ERRP_GUARD();
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PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
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CPUPPCState *env = &cpu->env;
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@ -224,8 +225,8 @@ static void cap_dfp_apply(SpaprMachineState *spapr, uint8_t val, Error **errp)
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return;
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}
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if (!(env->insns_flags2 & PPC2_DFP)) {
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error_setg(errp, "DFP support not available,"
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" try appending -machine cap-dfp=off");
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error_setg(errp, "DFP support not available");
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error_append_hint(errp, "Try appending -machine cap-dfp=off\n");
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}
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}
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@ -239,6 +240,7 @@ SpaprCapPossible cap_cfpc_possible = {
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static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val,
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Error **errp)
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{
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ERRP_GUARD();
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uint8_t kvm_val = kvmppc_get_cap_safe_cache();
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if (tcg_enabled() && val) {
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@ -247,9 +249,9 @@ static void cap_safe_cache_apply(SpaprMachineState *spapr, uint8_t val,
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cap_cfpc_possible.vals[val]);
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} else if (kvm_enabled() && (val > kvm_val)) {
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error_setg(errp,
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"Requested safe cache capability level not supported by kvm,"
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" try appending -machine cap-cfpc=%s",
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cap_cfpc_possible.vals[kvm_val]);
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"Requested safe cache capability level not supported by KVM");
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error_append_hint(errp, "Try appending -machine cap-cfpc=%s\n",
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cap_cfpc_possible.vals[kvm_val]);
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}
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}
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@ -263,6 +265,7 @@ SpaprCapPossible cap_sbbc_possible = {
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static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val,
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Error **errp)
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{
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ERRP_GUARD();
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uint8_t kvm_val = kvmppc_get_cap_safe_bounds_check();
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if (tcg_enabled() && val) {
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@ -271,9 +274,9 @@ static void cap_safe_bounds_check_apply(SpaprMachineState *spapr, uint8_t val,
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cap_sbbc_possible.vals[val]);
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} else if (kvm_enabled() && (val > kvm_val)) {
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error_setg(errp,
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"Requested safe bounds check capability level not supported by kvm,"
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" try appending -machine cap-sbbc=%s",
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cap_sbbc_possible.vals[kvm_val]);
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"Requested safe bounds check capability level not supported by KVM");
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error_append_hint(errp, "Try appending -machine cap-sbbc=%s\n",
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cap_sbbc_possible.vals[kvm_val]);
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}
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}
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@ -290,6 +293,7 @@ SpaprCapPossible cap_ibs_possible = {
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static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr,
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uint8_t val, Error **errp)
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{
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ERRP_GUARD();
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uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch();
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if (tcg_enabled() && val) {
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@ -298,9 +302,9 @@ static void cap_safe_indirect_branch_apply(SpaprMachineState *spapr,
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cap_ibs_possible.vals[val]);
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} else if (kvm_enabled() && (val > kvm_val)) {
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error_setg(errp,
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"Requested safe indirect branch capability level not supported by kvm,"
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" try appending -machine cap-ibs=%s",
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cap_ibs_possible.vals[kvm_val]);
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"Requested safe indirect branch capability level not supported by KVM");
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error_append_hint(errp, "Try appending -machine cap-ibs=%s\n",
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cap_ibs_possible.vals[kvm_val]);
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}
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}
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@ -377,23 +381,35 @@ static void cap_hpt_maxpagesize_cpu_apply(SpaprMachineState *spapr,
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static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
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uint8_t val, Error **errp)
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{
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ERRP_GUARD();
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PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
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if (!val) {
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/* capability disabled by default */
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return;
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}
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if (tcg_enabled()) {
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error_setg(errp,
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"No Nested KVM-HV support in tcg,"
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" try appending -machine cap-nested-hv=off");
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error_setg(errp, "No Nested KVM-HV support in TCG");
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error_append_hint(errp, "Try appending -machine cap-nested-hv=off\n");
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} else if (kvm_enabled()) {
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if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
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spapr->max_compat_pvr)) {
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error_setg(errp, "Nested KVM-HV only supported on POWER9");
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error_append_hint(errp,
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"Try appending -machine max-cpu-compat=power9\n");
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return;
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}
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if (!kvmppc_has_cap_nested_kvm_hv()) {
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error_setg(errp,
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"KVM implementation does not support Nested KVM-HV,"
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" try appending -machine cap-nested-hv=off");
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"KVM implementation does not support Nested KVM-HV");
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error_append_hint(errp,
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"Try appending -machine cap-nested-hv=off\n");
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} else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) {
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error_setg(errp,
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"Error enabling cap-nested-hv with KVM, try cap-nested-hv=off");
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error_setg(errp, "Error enabling cap-nested-hv with KVM");
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error_append_hint(errp,
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"Try appending -machine cap-nested-hv=off\n");
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}
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}
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}
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@ -401,6 +417,7 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
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static void cap_large_decr_apply(SpaprMachineState *spapr,
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uint8_t val, Error **errp)
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{
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ERRP_GUARD();
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PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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@ -411,22 +428,23 @@ static void cap_large_decr_apply(SpaprMachineState *spapr,
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if (tcg_enabled()) {
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if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
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spapr->max_compat_pvr)) {
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error_setg(errp,
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"Large decrementer only supported on POWER9, try -cpu POWER9");
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error_setg(errp, "Large decrementer only supported on POWER9");
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error_append_hint(errp, "Try -cpu POWER9\n");
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return;
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}
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} else if (kvm_enabled()) {
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int kvm_nr_bits = kvmppc_get_cap_large_decr();
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if (!kvm_nr_bits) {
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error_setg(errp,
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"No large decrementer support,"
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" try appending -machine cap-large-decr=off");
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error_setg(errp, "No large decrementer support");
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error_append_hint(errp,
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"Try appending -machine cap-large-decr=off\n");
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} else if (pcc->lrg_decr_bits != kvm_nr_bits) {
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error_setg(errp,
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"KVM large decrementer size (%d) differs to model (%d),"
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" try appending -machine cap-large-decr=off",
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kvm_nr_bits, pcc->lrg_decr_bits);
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"KVM large decrementer size (%d) differs to model (%d)",
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kvm_nr_bits, pcc->lrg_decr_bits);
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error_append_hint(errp,
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"Try appending -machine cap-large-decr=off\n");
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}
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}
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}
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@ -435,14 +453,15 @@ static void cap_large_decr_cpu_apply(SpaprMachineState *spapr,
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PowerPCCPU *cpu,
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uint8_t val, Error **errp)
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{
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ERRP_GUARD();
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CPUPPCState *env = &cpu->env;
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target_ulong lpcr = env->spr[SPR_LPCR];
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if (kvm_enabled()) {
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if (kvmppc_enable_cap_large_decr(cpu, val)) {
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error_setg(errp,
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"No large decrementer support,"
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" try appending -machine cap-large-decr=off");
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error_setg(errp, "No large decrementer support");
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error_append_hint(errp,
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"Try appending -machine cap-large-decr=off\n");
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}
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}
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@ -457,6 +476,7 @@ static void cap_large_decr_cpu_apply(SpaprMachineState *spapr,
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static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val,
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Error **errp)
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{
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ERRP_GUARD();
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uint8_t kvm_val = kvmppc_get_cap_count_cache_flush_assist();
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if (tcg_enabled() && val) {
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@ -479,14 +499,15 @@ static void cap_ccf_assist_apply(SpaprMachineState *spapr, uint8_t val,
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return;
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}
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error_setg(errp,
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"Requested count cache flush assist capability level not supported by kvm,"
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" try appending -machine cap-ccf-assist=off");
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"Requested count cache flush assist capability level not supported by KVM");
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error_append_hint(errp, "Try appending -machine cap-ccf-assist=off\n");
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}
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}
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static void cap_fwnmi_apply(SpaprMachineState *spapr, uint8_t val,
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Error **errp)
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{
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ERRP_GUARD();
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if (!val) {
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return; /* Disabled by default */
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}
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@ -139,6 +139,7 @@ SpaprIrq spapr_irq_dual = {
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static int spapr_irq_check(SpaprMachineState *spapr, Error **errp)
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{
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ERRP_GUARD();
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MachineState *machine = MACHINE(spapr);
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/*
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@ -179,14 +180,19 @@ static int spapr_irq_check(SpaprMachineState *spapr, Error **errp)
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/*
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* On a POWER9 host, some older KVM XICS devices cannot be destroyed and
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* re-created. Detect that early to avoid QEMU to exit later when the
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* guest reboots.
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* re-created. Same happens with KVM nested guests. Detect that early to
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* avoid QEMU to exit later when the guest reboots.
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*/
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if (kvm_enabled() &&
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spapr->irq == &spapr_irq_dual &&
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kvm_kernel_irqchip_required() &&
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xics_kvm_has_broken_disconnect(spapr)) {
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error_setg(errp, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
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error_setg(errp,
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"KVM is incompatible with ic-mode=dual,kernel-irqchip=on");
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error_append_hint(errp,
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"This can happen with an old KVM or in a KVM nested guest.\n");
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error_append_hint(errp,
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"Try without kernel-irqchip or with kernel-irqchip=off.\n");
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return -1;
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}
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|
@ -1796,6 +1796,7 @@ static void spapr_phb_destroy_msi(gpointer opaque)
|
|||
|
||||
static void spapr_phb_realize(DeviceState *dev, Error **errp)
|
||||
{
|
||||
ERRP_GUARD();
|
||||
/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
|
||||
* tries to add a sPAPR PHB to a non-pseries machine.
|
||||
*/
|
||||
|
|
@ -1813,7 +1814,6 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
|
|||
uint64_t msi_window_size = 4096;
|
||||
SpaprTceTable *tcet;
|
||||
const unsigned windows_supported = spapr_phb_windows_supported(sphb);
|
||||
Error *local_err = NULL;
|
||||
|
||||
if (!spapr) {
|
||||
error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine");
|
||||
|
|
@ -1964,13 +1964,12 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
|
|||
|
||||
/* Initialize the LSI table */
|
||||
for (i = 0; i < PCI_NUM_PINS; i++) {
|
||||
uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
|
||||
int irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i;
|
||||
|
||||
if (smc->legacy_irq_allocation) {
|
||||
irq = spapr_irq_findone(spapr, &local_err);
|
||||
if (local_err) {
|
||||
error_propagate_prepend(errp, local_err,
|
||||
"can't allocate LSIs: ");
|
||||
irq = spapr_irq_findone(spapr, errp);
|
||||
if (irq < 0) {
|
||||
error_prepend(errp, "can't allocate LSIs: ");
|
||||
/*
|
||||
* Older machines will never support PHB hotplug, ie, this is an
|
||||
* init only path and QEMU will terminate. No need to rollback.
|
||||
|
|
@ -1979,9 +1978,8 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
|
|||
}
|
||||
}
|
||||
|
||||
spapr_irq_claim(spapr, irq, true, &local_err);
|
||||
if (local_err) {
|
||||
error_propagate_prepend(errp, local_err, "can't allocate LSIs: ");
|
||||
if (spapr_irq_claim(spapr, irq, true, errp) < 0) {
|
||||
error_prepend(errp, "can't allocate LSIs: ");
|
||||
goto unrealize;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue