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target-xtensa: add FP registers

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There are 16 32-bit FP registers (f0 - f15), control and status user
registers (fcr, fsr).

See ISA, 4.3.10 for more details.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Max Filippov 2012-09-19 04:23:54 +04:00 • committed by Blue Swirl
parent b81fe822da
commit dd519cbec6
5 changed files with 71 additions and 7 deletions
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3
target-xtensa/cpu.h
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@ -36,6 +36,7 @@
#include "config.h"
#include "qemu-common.h"
#include "cpu-defs.h"
#include "fpu/softfloat.h"
#define TARGET_HAS_ICE 1
@ -325,6 +326,8 @@ typedef struct CPUXtensaState {
uint32_t sregs[256];
uint32_t uregs[256];
uint32_t phys_regs[MAX_NAREG];
float32 fregs[16];
float_status fp_status;
xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];