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target/ppc: support for 32-bit carry and overflow

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POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
and corresponding defines.

Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
is updated.

Arithmetic instructions:
    * Addition and Substractions:

        addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme,
        addze, and subfze always updates CA and CA32.

        => CA reflects the carry out of bit 0 in 64-bit mode and out of
           bit 32 in 32-bit mode.
        => CA32 reflects the carry out of bit 32 independent of the
           mode.

        => SO and OV reflects overflow of the 64-bit result in 64-bit
           mode and overflow of the low-order 32-bit result in 32-bit
           mode
        => OV32 reflects overflow of the low-order 32-bit independent of
           the mode

    * Multiply Low and Divide:

        For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits
        reflects overflow of the 64-bit result

        For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits
        reflects overflow of the 32-bit result

     * Negate with OE=1 (nego)

       For 64-bit mode if the register RA contains
       0x8000_0000_0000_0000, OV and OV32 are set to 1.

       For 32-bit mode if the register RA contains 0x8000_0000, OV and
       OV32 are set to 1.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nikunj A Dadhania 2017-02-27 10:27:54 +05:30 • committed by David Gibson
parent e78308fd39
commit dd09c36159
4 changed files with 38 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

21
target/ppc/translate.c
View file

@ -71,7 +71,7 @@ static TCGv cpu_lr;
#if defined(TARGET_PPC64)
static TCGv cpu_cfar;
#endif
static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32;
static TCGv cpu_reserve;
static TCGv cpu_fpscr;
static TCGv_i32 cpu_access_type;
@ -173,6 +173,10 @@ void ppc_translate_init(void)
offsetof(CPUPPCState, ov), "OV");
cpu_ca = tcg_global_mem_new(cpu_env,
offsetof(CPUPPCState, ca), "CA");
cpu_ov32 = tcg_global_mem_new(cpu_env,
offsetof(CPUPPCState, ov32), "OV32");
cpu_ca32 = tcg_global_mem_new(cpu_env,
offsetof(CPUPPCState, ca32), "CA32");
cpu_reserve = tcg_global_mem_new(cpu_env,
offsetof(CPUPPCState, reserve_addr),
@ -3703,7 +3707,7 @@ static void gen_tdi(DisasContext *ctx)
/*** Processor control ***/
static void gen_read_xer(TCGv dst)
static void gen_read_xer(DisasContext *ctx, TCGv dst)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@ -3715,6 +3719,12 @@ static void gen_read_xer(TCGv dst)
tcg_gen_or_tl(t0, t0, t1);
tcg_gen_or_tl(dst, dst, t2);
tcg_gen_or_tl(dst, dst, t0);
if (is_isa300(ctx)) {
tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
tcg_gen_or_tl(dst, dst, t0);
tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
tcg_gen_or_tl(dst, dst, t0);
}
tcg_temp_free(t0);
tcg_temp_free(t1);
tcg_temp_free(t2);
@ -3722,8 +3732,13 @@ static void gen_read_xer(TCGv dst)
static void gen_write_xer(TCGv src)
{
/* Write all flags, while reading back check for isa300 */
tcg_gen_andi_tl(cpu_xer, src,
~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
~((1u << XER_SO) |
(1u << XER_OV) | (1u << XER_OV32) |
(1u << XER_CA) | (1u << XER_CA32)));
tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);