pcie: Add a helper to declare the PRI capability for a pcie device

Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
Message-Id: <20250520071823.764266-5-clement.mathieu--drif@eviden.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
CLEMENT MATHIEU--DRIF 2025-05-20 07:18:54 +00:00 committed by Michael S. Tsirkin
parent 6a3ae6a244
commit dcad6cb2ab
3 changed files with 33 additions and 1 deletions

View file

@ -70,9 +70,10 @@ struct PCIExpressDevice {
uint16_t aer_cap;
PCIEAERLog aer_log;
/* Offset of ATS and PASID capabilities in config space */
/* Offset of ATS, PRI and PASID capabilities in config space */
uint16_t ats_cap;
uint16_t pasid_cap;
uint16_t pri_cap;
/* ACS */
uint16_t acs_cap;
@ -154,6 +155,8 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
bool exec_perm, bool priv_mod);
void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_pr_cap,
bool prg_response_pasid_req);
bool pcie_pasid_enabled(const PCIDevice *dev);
bool pcie_ats_enabled(const PCIDevice *dev);

View file

@ -91,6 +91,9 @@ typedef enum PCIExpLinkWidth {
#define PCI_EXT_CAP_PASID_MAX_WIDTH 20
#define PCI_PASID_CAP_WIDTH_SHIFT 8
/* PRI */
#define PCI_PRI_VER 1
/* AER */
#define PCI_ERR_VER 2
#define PCI_ERR_SIZEOF 0x48