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pcie: Add a helper to declare the PRI capability for a pcie device
Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-5-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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3 changed files with 33 additions and 1 deletions
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@ -70,9 +70,10 @@ struct PCIExpressDevice {
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uint16_t aer_cap;
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PCIEAERLog aer_log;
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/* Offset of ATS and PASID capabilities in config space */
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/* Offset of ATS, PRI and PASID capabilities in config space */
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uint16_t ats_cap;
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uint16_t pasid_cap;
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uint16_t pri_cap;
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/* ACS */
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uint16_t acs_cap;
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@ -154,6 +155,8 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
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void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
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bool exec_perm, bool priv_mod);
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void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_pr_cap,
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bool prg_response_pasid_req);
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bool pcie_pasid_enabled(const PCIDevice *dev);
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bool pcie_ats_enabled(const PCIDevice *dev);
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@ -91,6 +91,9 @@ typedef enum PCIExpLinkWidth {
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#define PCI_EXT_CAP_PASID_MAX_WIDTH 20
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#define PCI_PASID_CAP_WIDTH_SHIFT 8
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/* PRI */
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#define PCI_PRI_VER 1
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/* AER */
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#define PCI_ERR_VER 2
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#define PCI_ERR_SIZEOF 0x48
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