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riscv: spike: Remove target macro conditionals

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 04ac7fba2348c92f296a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2020-12-16 10:22:32 -08:00
parent c0a635f397
commit dc4d4aaee3
2 changed files with 1 additions and 7 deletions
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6
include/hw/riscv/spike.h
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@ -47,10 +47,4 @@ enum {
SPIKE_DRAM
};
#if defined(TARGET_RISCV32)
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
#endif
#endif