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target/arm/kvm: Move kvm_arm_get_host_cpu_features and unexport
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
21beccd384
commit
dc40d45ebd
3 changed files with 265 additions and 276 deletions
265
target/arm/kvm.c
265
target/arm/kvm.c
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@ -41,6 +41,17 @@ static bool cap_has_mp_state;
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static bool cap_has_inject_serror_esr;
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static bool cap_has_inject_serror_esr;
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static bool cap_has_inject_ext_dabt;
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static bool cap_has_inject_ext_dabt;
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/**
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* ARMHostCPUFeatures: information about the host CPU (identified
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* by asking the host kernel)
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*/
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typedef struct ARMHostCPUFeatures {
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ARMISARegisters isar;
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uint64_t features;
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uint32_t target;
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const char *dtb_compatible;
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} ARMHostCPUFeatures;
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static ARMHostCPUFeatures arm_host_cpu_features;
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static ARMHostCPUFeatures arm_host_cpu_features;
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int kvm_arm_vcpu_init(CPUState *cs)
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int kvm_arm_vcpu_init(CPUState *cs)
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@ -167,6 +178,260 @@ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray)
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}
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}
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}
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}
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static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
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{
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uint64_t ret;
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struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
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int err;
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assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
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err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
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if (err < 0) {
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return -1;
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}
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*pret = ret;
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return 0;
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}
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static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
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{
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struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
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assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
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return ioctl(fd, KVM_GET_ONE_REG, &idreg);
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}
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static bool kvm_arm_pauth_supported(void)
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{
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return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) &&
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kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
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}
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static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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{
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/* Identify the feature bits corresponding to the host CPU, and
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* fill out the ARMHostCPUClass fields accordingly. To do this
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* we have to create a scratch VM, create a single CPU inside it,
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* and then query that CPU for the relevant ID registers.
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*/
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int fdarray[3];
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bool sve_supported;
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bool pmu_supported = false;
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uint64_t features = 0;
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int err;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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* we know these will only support creating one kind of guest CPU,
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* which is its preferred CPU type. Fortunately these old kernels
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* support only a very limited number of CPUs.
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*/
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static const uint32_t cpus_to_try[] = {
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KVM_ARM_TARGET_AEM_V8,
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KVM_ARM_TARGET_FOUNDATION_V8,
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KVM_ARM_TARGET_CORTEX_A57,
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QEMU_KVM_ARM_TARGET_NONE
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};
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/*
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* target = -1 informs kvm_arm_create_scratch_host_vcpu()
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* to use the preferred target
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*/
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struct kvm_vcpu_init init = { .target = -1, };
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/*
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* Ask for SVE if supported, so that we can query ID_AA64ZFR0,
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* which is otherwise RAZ.
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*/
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sve_supported = kvm_arm_sve_supported();
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if (sve_supported) {
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init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
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}
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/*
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* Ask for Pointer Authentication if supported, so that we get
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* the unsanitized field values for AA64ISAR1_EL1.
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*/
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if (kvm_arm_pauth_supported()) {
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init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
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1 << KVM_ARM_VCPU_PTRAUTH_GENERIC);
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}
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if (kvm_arm_pmu_supported()) {
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init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
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pmu_supported = true;
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}
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if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
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return false;
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}
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ahcf->target = init.target;
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ahcf->dtb_compatible = "arm,arm-v8";
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err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 0));
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if (unlikely(err < 0)) {
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/*
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* Before v4.15, the kernel only exposed a limited number of system
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* registers, not including any of the interesting AArch64 ID regs.
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* For the most part we could leave these fields as zero with minimal
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* effect, since this does not affect the values seen by the guest.
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*
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* However, it could cause problems down the line for QEMU,
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* so provide a minimal v8.0 default.
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*
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* ??? Could read MIDR and use knowledge from cpu64.c.
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* ??? Could map a page of memory into our temp guest and
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* run the tiniest of hand-crafted kernels to extract
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* the values seen by the guest.
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* ??? Either of these sounds like too much effort just
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* to work around running a modern host kernel.
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*/
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ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
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err = 0;
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} else {
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
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ARM64_SYS_REG(3, 0, 0, 4, 1));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 5));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
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ARM64_SYS_REG(3, 0, 0, 5, 0));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
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ARM64_SYS_REG(3, 0, 0, 5, 1));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
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ARM64_SYS_REG(3, 0, 0, 6, 0));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
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ARM64_SYS_REG(3, 0, 0, 6, 1));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
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ARM64_SYS_REG(3, 0, 0, 6, 2));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
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ARM64_SYS_REG(3, 0, 0, 7, 0));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
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ARM64_SYS_REG(3, 0, 0, 7, 1));
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
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ARM64_SYS_REG(3, 0, 0, 7, 2));
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/*
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* Note that if AArch32 support is not present in the host,
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* the AArch32 sysregs are present to be read, but will
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* return UNKNOWN values. This is neither better nor worse
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* than skipping the reads and leaving 0, as we must avoid
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* considering the values in every case.
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*/
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
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ARM64_SYS_REG(3, 0, 0, 1, 0));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
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ARM64_SYS_REG(3, 0, 0, 1, 1));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
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ARM64_SYS_REG(3, 0, 0, 1, 2));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
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ARM64_SYS_REG(3, 0, 0, 1, 4));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
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ARM64_SYS_REG(3, 0, 0, 1, 5));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
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ARM64_SYS_REG(3, 0, 0, 1, 6));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
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ARM64_SYS_REG(3, 0, 0, 1, 7));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
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ARM64_SYS_REG(3, 0, 0, 2, 0));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
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ARM64_SYS_REG(3, 0, 0, 2, 1));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
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ARM64_SYS_REG(3, 0, 0, 2, 2));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
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ARM64_SYS_REG(3, 0, 0, 2, 3));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
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ARM64_SYS_REG(3, 0, 0, 2, 4));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
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ARM64_SYS_REG(3, 0, 0, 2, 5));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
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ARM64_SYS_REG(3, 0, 0, 2, 6));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
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ARM64_SYS_REG(3, 0, 0, 2, 7));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
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ARM64_SYS_REG(3, 0, 0, 3, 0));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
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ARM64_SYS_REG(3, 0, 0, 3, 1));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
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ARM64_SYS_REG(3, 0, 0, 3, 2));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
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ARM64_SYS_REG(3, 0, 0, 3, 4));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
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ARM64_SYS_REG(3, 0, 0, 3, 5));
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err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
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ARM64_SYS_REG(3, 0, 0, 3, 6));
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/*
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* DBGDIDR is a bit complicated because the kernel doesn't
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* provide an accessor for it in 64-bit mode, which is what this
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* scratch VM is in, and there's no architected "64-bit sysreg
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* which reads the same as the 32-bit register" the way there is
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* for other ID registers. Instead we synthesize a value from the
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* AArch64 ID_AA64DFR0, the same way the kernel code in
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* arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
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* We only do this if the CPU supports AArch32 at EL1.
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*/
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if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
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int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
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int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
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int ctx_cmps =
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FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
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int version = 6; /* ARMv8 debug architecture */
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bool has_el3 =
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!!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
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uint32_t dbgdidr = 0;
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dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
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dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps);
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dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps);
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dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version);
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dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3);
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dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3);
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dbgdidr |= (1 << 15); /* RES1 bit */
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ahcf->isar.dbgdidr = dbgdidr;
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}
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if (pmu_supported) {
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/* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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if (sve_supported) {
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't
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* expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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* enabled SVE support, which resulted in an error rather than RAZ.
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* So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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}
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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if (err < 0) {
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return false;
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}
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/*
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* We can assume any KVM supporting CPU is at least a v8
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* with VFPv4+Neon; this in turn implies most of the other
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* feature bits.
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*/
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features |= 1ULL << ARM_FEATURE_V8;
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features |= 1ULL << ARM_FEATURE_NEON;
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features |= 1ULL << ARM_FEATURE_AARCH64;
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features |= 1ULL << ARM_FEATURE_PMU;
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features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
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ahcf->features = features;
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return true;
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}
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void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
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void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
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{
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{
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CPUARMState *env = &cpu->env;
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CPUARMState *env = &cpu->env;
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@ -143,260 +143,6 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa)
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}
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}
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}
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}
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static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
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{
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uint64_t ret;
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struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)&ret };
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int err;
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assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
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err = ioctl(fd, KVM_GET_ONE_REG, &idreg);
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if (err < 0) {
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return -1;
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}
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*pret = ret;
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return 0;
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}
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static int read_sys_reg64(int fd, uint64_t *pret, uint64_t id)
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{
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struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
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assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64);
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|
||||||
return ioctl(fd, KVM_GET_ONE_REG, &idreg);
|
|
||||||
}
|
|
||||||
|
|
||||||
static bool kvm_arm_pauth_supported(void)
|
|
||||||
{
|
|
||||||
return (kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_ADDRESS) &&
|
|
||||||
kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
|
|
||||||
}
|
|
||||||
|
|
||||||
bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
|
|
||||||
{
|
|
||||||
/* Identify the feature bits corresponding to the host CPU, and
|
|
||||||
* fill out the ARMHostCPUClass fields accordingly. To do this
|
|
||||||
* we have to create a scratch VM, create a single CPU inside it,
|
|
||||||
* and then query that CPU for the relevant ID registers.
|
|
||||||
*/
|
|
||||||
int fdarray[3];
|
|
||||||
bool sve_supported;
|
|
||||||
bool pmu_supported = false;
|
|
||||||
uint64_t features = 0;
|
|
||||||
int err;
|
|
||||||
|
|
||||||
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
|
|
||||||
* we know these will only support creating one kind of guest CPU,
|
|
||||||
* which is its preferred CPU type. Fortunately these old kernels
|
|
||||||
* support only a very limited number of CPUs.
|
|
||||||
*/
|
|
||||||
static const uint32_t cpus_to_try[] = {
|
|
||||||
KVM_ARM_TARGET_AEM_V8,
|
|
||||||
KVM_ARM_TARGET_FOUNDATION_V8,
|
|
||||||
KVM_ARM_TARGET_CORTEX_A57,
|
|
||||||
QEMU_KVM_ARM_TARGET_NONE
|
|
||||||
};
|
|
||||||
/*
|
|
||||||
* target = -1 informs kvm_arm_create_scratch_host_vcpu()
|
|
||||||
* to use the preferred target
|
|
||||||
*/
|
|
||||||
struct kvm_vcpu_init init = { .target = -1, };
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Ask for SVE if supported, so that we can query ID_AA64ZFR0,
|
|
||||||
* which is otherwise RAZ.
|
|
||||||
*/
|
|
||||||
sve_supported = kvm_arm_sve_supported();
|
|
||||||
if (sve_supported) {
|
|
||||||
init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Ask for Pointer Authentication if supported, so that we get
|
|
||||||
* the unsanitized field values for AA64ISAR1_EL1.
|
|
||||||
*/
|
|
||||||
if (kvm_arm_pauth_supported()) {
|
|
||||||
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
|
|
||||||
1 << KVM_ARM_VCPU_PTRAUTH_GENERIC);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (kvm_arm_pmu_supported()) {
|
|
||||||
init.features[0] |= 1 << KVM_ARM_VCPU_PMU_V3;
|
|
||||||
pmu_supported = true;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
ahcf->target = init.target;
|
|
||||||
ahcf->dtb_compatible = "arm,arm-v8";
|
|
||||||
|
|
||||||
err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 4, 0));
|
|
||||||
if (unlikely(err < 0)) {
|
|
||||||
/*
|
|
||||||
* Before v4.15, the kernel only exposed a limited number of system
|
|
||||||
* registers, not including any of the interesting AArch64 ID regs.
|
|
||||||
* For the most part we could leave these fields as zero with minimal
|
|
||||||
* effect, since this does not affect the values seen by the guest.
|
|
||||||
*
|
|
||||||
* However, it could cause problems down the line for QEMU,
|
|
||||||
* so provide a minimal v8.0 default.
|
|
||||||
*
|
|
||||||
* ??? Could read MIDR and use knowledge from cpu64.c.
|
|
||||||
* ??? Could map a page of memory into our temp guest and
|
|
||||||
* run the tiniest of hand-crafted kernels to extract
|
|
||||||
* the values seen by the guest.
|
|
||||||
* ??? Either of these sounds like too much effort just
|
|
||||||
* to work around running a modern host kernel.
|
|
||||||
*/
|
|
||||||
ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
|
|
||||||
err = 0;
|
|
||||||
} else {
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 4, 1));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 4, 5));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 5, 0));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 5, 1));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 6, 0));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 6, 1));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 6, 2));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 7, 0));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 7, 1));
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 7, 2));
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Note that if AArch32 support is not present in the host,
|
|
||||||
* the AArch32 sysregs are present to be read, but will
|
|
||||||
* return UNKNOWN values. This is neither better nor worse
|
|
||||||
* than skipping the reads and leaving 0, as we must avoid
|
|
||||||
* considering the values in every case.
|
|
||||||
*/
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 1, 0));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 1, 1));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 1, 2));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 1, 4));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 1, 5));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 1, 6));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 1, 7));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 2, 0));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 2, 1));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 2, 2));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 2, 3));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 2, 4));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 2, 5));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 2, 6));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 2, 7));
|
|
||||||
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 3, 0));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 3, 1));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 3, 2));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 3, 4));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 3, 5));
|
|
||||||
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 3, 6));
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DBGDIDR is a bit complicated because the kernel doesn't
|
|
||||||
* provide an accessor for it in 64-bit mode, which is what this
|
|
||||||
* scratch VM is in, and there's no architected "64-bit sysreg
|
|
||||||
* which reads the same as the 32-bit register" the way there is
|
|
||||||
* for other ID registers. Instead we synthesize a value from the
|
|
||||||
* AArch64 ID_AA64DFR0, the same way the kernel code in
|
|
||||||
* arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
|
|
||||||
* We only do this if the CPU supports AArch32 at EL1.
|
|
||||||
*/
|
|
||||||
if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
|
|
||||||
int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
|
|
||||||
int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
|
|
||||||
int ctx_cmps =
|
|
||||||
FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
|
|
||||||
int version = 6; /* ARMv8 debug architecture */
|
|
||||||
bool has_el3 =
|
|
||||||
!!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
|
|
||||||
uint32_t dbgdidr = 0;
|
|
||||||
|
|
||||||
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
|
|
||||||
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps);
|
|
||||||
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps);
|
|
||||||
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version);
|
|
||||||
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3);
|
|
||||||
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3);
|
|
||||||
dbgdidr |= (1 << 15); /* RES1 bit */
|
|
||||||
ahcf->isar.dbgdidr = dbgdidr;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (pmu_supported) {
|
|
||||||
/* PMCR_EL0 is only accessible if the vCPU has feature PMU_V3 */
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
|
|
||||||
ARM64_SYS_REG(3, 3, 9, 12, 0));
|
|
||||||
}
|
|
||||||
|
|
||||||
if (sve_supported) {
|
|
||||||
/*
|
|
||||||
* There is a range of kernels between kernel commit 73433762fcae
|
|
||||||
* and f81cb2c3ad41 which have a bug where the kernel doesn't
|
|
||||||
* expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
|
|
||||||
* enabled SVE support, which resulted in an error rather than RAZ.
|
|
||||||
* So only read the register if we set KVM_ARM_VCPU_SVE above.
|
|
||||||
*/
|
|
||||||
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
|
|
||||||
ARM64_SYS_REG(3, 0, 0, 4, 4));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
kvm_arm_destroy_scratch_host_vcpu(fdarray);
|
|
||||||
|
|
||||||
if (err < 0) {
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* We can assume any KVM supporting CPU is at least a v8
|
|
||||||
* with VFPv4+Neon; this in turn implies most of the other
|
|
||||||
* feature bits.
|
|
||||||
*/
|
|
||||||
features |= 1ULL << ARM_FEATURE_V8;
|
|
||||||
features |= 1ULL << ARM_FEATURE_NEON;
|
|
||||||
features |= 1ULL << ARM_FEATURE_AARCH64;
|
|
||||||
features |= 1ULL << ARM_FEATURE_PMU;
|
|
||||||
features |= 1ULL << ARM_FEATURE_GENERIC_TIMER;
|
|
||||||
|
|
||||||
ahcf->features = features;
|
|
||||||
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
|
|
||||||
void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
|
void kvm_arm_steal_time_finalize(ARMCPU *cpu, Error **errp)
|
||||||
{
|
{
|
||||||
bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME);
|
bool has_steal_time = kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME);
|
||||||
|
|
|
||||||
|
|
@ -214,28 +214,6 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
|
||||||
*/
|
*/
|
||||||
void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
|
void kvm_arm_destroy_scratch_host_vcpu(int *fdarray);
|
||||||
|
|
||||||
/**
|
|
||||||
* ARMHostCPUFeatures: information about the host CPU (identified
|
|
||||||
* by asking the host kernel)
|
|
||||||
*/
|
|
||||||
typedef struct ARMHostCPUFeatures {
|
|
||||||
ARMISARegisters isar;
|
|
||||||
uint64_t features;
|
|
||||||
uint32_t target;
|
|
||||||
const char *dtb_compatible;
|
|
||||||
} ARMHostCPUFeatures;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* kvm_arm_get_host_cpu_features:
|
|
||||||
* @ahcf: ARMHostCPUClass to fill in
|
|
||||||
*
|
|
||||||
* Probe the capabilities of the host kernel's preferred CPU and fill
|
|
||||||
* in the ARMHostCPUClass struct accordingly.
|
|
||||||
*
|
|
||||||
* Returns true on success and false otherwise.
|
|
||||||
*/
|
|
||||||
bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* kvm_arm_sve_get_vls:
|
* kvm_arm_sve_get_vls:
|
||||||
* @cs: CPUState
|
* @cs: CPUState
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue