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aspeed: extend the number of host SPI controllers

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The AST2500 SoC has two. Let's prepare ground for the next changes
which will add the required definitions for the second host SPI
controller.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1474977462-28032-4-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater 2016-10-17 19:22:16 +01:00 • committed by Peter Maydell
parent dcb834447f
commit dbcabeeb54
3 changed files with 35 additions and 17 deletions
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6
include/hw/arm/aspeed_soc.h
View file

@ -20,6 +20,8 @@
#include "hw/i2c/aspeed_i2c.h"
#include "hw/ssi/aspeed_smc.h"
#define ASPEED_SPIS_NUM 2
typedef struct AspeedSoCState {
/*< private >*/
DeviceState parent;
@ -32,7 +34,7 @@ typedef struct AspeedSoCState {
AspeedI2CState i2c;
AspeedSCUState scu;
AspeedSMCState fmc;
AspeedSMCState spi;
AspeedSMCState spi[ASPEED_SPIS_NUM];
AspeedSDMCState sdmc;
} AspeedSoCState;
@ -44,6 +46,8 @@ typedef struct AspeedSoCInfo {
const char *cpu_model;
uint32_t silicon_rev;
hwaddr sdram_base;
int spis_num;
const hwaddr *spi_bases;
} AspeedSoCInfo;
typedef struct AspeedSoCClass {