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Misc HW patches

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- Use qemu_hexdump_line() in TPM backend (Philippe)
 - Remove magic number in APIC (Phil)
 - Disable thread-level cache topology (Zhao)
 - Xen QOM style cleanups (Bernhard)
 - Introduce TYPE_DYNAMIC_SYS_BUS_DEVICE (Philippe)
 - Invert logic of machine no_sdcard flag (Philippe)
 - Housekeeping in MicroBlaze functional tests (Philippe)
 - Prevent out-of-bound access in SMC91C111 RX path (Peter)
 - Declare more fields / arguments as const (Philippe)
 - Introduce EndianMode QAPI enum (Philippe)
 - Make various Xilinx devices endianness configurable (Philippe)
 - Mark some devices memory regions as little-endian (Philippe)
 - Allow execution RX gdbsim machine without BIOS/kernel (Keith)
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Merge tag 'hw-misc-20250216' of https://github.com/philmd/qemu into staging

Misc HW patches

- Use qemu_hexdump_line() in TPM backend (Philippe)
- Remove magic number in APIC (Phil)
- Disable thread-level cache topology (Zhao)
- Xen QOM style cleanups (Bernhard)
- Introduce TYPE_DYNAMIC_SYS_BUS_DEVICE (Philippe)
- Invert logic of machine no_sdcard flag (Philippe)
- Housekeeping in MicroBlaze functional tests (Philippe)
- Prevent out-of-bound access in SMC91C111 RX path (Peter)
- Declare more fields / arguments as const (Philippe)
- Introduce EndianMode QAPI enum (Philippe)
- Make various Xilinx devices endianness configurable (Philippe)
- Mark some devices memory regions as little-endian (Philippe)
- Allow execution RX gdbsim machine without BIOS/kernel (Keith)

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# gpg: Signature made Sun 16 Feb 2025 15:58:55 EST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20250216' of https://github.com/philmd/qemu: (39 commits)
  hw/rx: Allow execution without either bios or kernel
  hw/pci-host: Mark versatile regions as little-endian
  hw/mips: Mark Loonson3 Virt machine devices as little-endian
  hw/mips: Mark Boston machine devices as little-endian
  hw/arm: Mark Allwinner Technology devices as little-endian
  hw/ssi/xilinx_spi: Make device endianness configurable
  hw/char/xilinx_uartlite: Make device endianness configurable
  hw/timer/xilinx_timer: Make device endianness configurable
  hw/net/xilinx_ethlite: Make device endianness configurable
  hw/intc/xilinx_intc: Make device endianness configurable
  hw/qdev-properties-system: Introduce EndianMode QAPI enum
  hw: Make class data 'const'
  hw: Declare various const data as 'const'
  tests/functional: Remove sleep() kludges from microblaze tests
  tests/functional: Allow microblaze tests to take a machine name argument
  tests/functional: Explicit endianness of microblaze assets
  hw/net/smc91c111: Ignore attempt to pop from empty RX fifo
  hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header
  hw/boards: Ensure machine setting auto_create_sdcard expose a SD Bus
  hw/riscv: Remove all invalid uses of auto_create_sdcard=true
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-02-16 20:48:06 -05:00
commit db7aa99ef8
100 changed files with 425 additions and 281 deletions
Download patch file Download diff file Expand all files Collapse all files

24
backends/tpm/tpm_util.c
View file

@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "tpm_int.h"
@ -336,8 +337,8 @@ void tpm_sized_buffer_reset(TPMSizedBuffer *tsb)
void tpm_util_show_buffer(const unsigned char *buffer,
size_t buffer_size, const char *string)
{
size_t len, i;
char *line_buffer, *p;
g_autoptr(GString) str = NULL;
size_t len, i, l;
if (!trace_event_get_state_backends(TRACE_TPM_UTIL_SHOW_BUFFER_CONTENT)) {
return;
@ -345,19 +346,14 @@ void tpm_util_show_buffer(const unsigned char *buffer,
len = MIN(tpm_cmd_get_size(buffer), buffer_size);
trace_tpm_util_show_buffer_header(string, len);
/*
* allocate enough room for 3 chars per buffer entry plus a
* newline after every 16 chars and a final null terminator.
*/
line_buffer = g_malloc(len * 3 + (len / 16) + 1);
for (i = 0, p = line_buffer; i < len; i++) {
if (i && !(i % 16)) {
p += sprintf(p, "\n");
for (i = 0; i < len; i += l) {
if (str) {
g_string_append_c(str, '\n');
}
p += sprintf(p, "%.2X ", buffer[i]);
l = MIN(len, 16);
str = qemu_hexdump_line(str, buffer, l, 1, 0);
}
trace_tpm_util_show_buffer_content(line_buffer);
g_free(line_buffer);
g_string_ascii_up(str);
trace_tpm_util_show_buffer_content(str->str);
}

2
hw/arm/allwinner-a10.c
View file

@ -158,7 +158,7 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
/* FIXME use a qdev chardev prop instead of serial_hd() */
serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2,
qdev_get_gpio_in(dev, 1),
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);

8
hw/arm/allwinner-h3.c
View file

@ -408,19 +408,19 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
/* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
/* UART1 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
115200, serial_hd(1), DEVICE_LITTLE_ENDIAN);
/* UART2 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
115200, serial_hd(2), DEVICE_LITTLE_ENDIAN);
/* UART3 */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
115200, serial_hd(3), DEVICE_LITTLE_ENDIAN);
/* DRAMC */
sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);

2
hw/arm/allwinner-r40.c
View file

@ -492,7 +492,7 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
serial_mm_init(get_system_memory(), addr, 2,
qdev_get_gpio_in(DEVICE(&s->gic), uart_irqs[i]),
115200, serial_hd(i), DEVICE_NATIVE_ENDIAN);
115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
}
/* I2C */

20
hw/arm/aspeed.c
View file

@ -1253,6 +1253,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635f";
amc->num_cs = 1;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 256 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1269,6 +1270,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635e";
amc->num_cs = 1;
amc->i2c_init = quanta_q71l_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 128 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
}
@ -1287,6 +1289,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
amc->num_cs = 1;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 256 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
}
@ -1305,6 +1308,7 @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
amc->num_cs = 1;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = palmetto_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
}
@ -1321,6 +1325,7 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635f";
amc->num_cs = 1;
amc->i2c_init = ast2500_evb_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1338,6 +1343,7 @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635e";
amc->num_cs = 2;
amc->i2c_init = yosemitev2_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1354,6 +1360,7 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx66l1g45g";
amc->num_cs = 2;
amc->i2c_init = romulus_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1371,6 +1378,7 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635e";
amc->num_cs = 2;
amc->i2c_init = tiogapass_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1387,6 +1395,7 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx66l1g45g";
amc->num_cs = 2;
amc->i2c_init = sonorapass_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1403,6 +1412,7 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx66l1g45g";
amc->num_cs = 2;
amc->i2c_init = witherspoon_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1423,6 +1433,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
ASPEED_MAC3_ON;
amc->sdhci_wp_inverted = true;
amc->i2c_init = ast2600_evb_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
aspeed_machine_ast2600_class_emmc_init(oc);
@ -1441,6 +1452,7 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = g220a_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1024 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1458,6 +1470,7 @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = fp5280g2_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1476,6 +1489,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = rainier_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
aspeed_machine_ast2600_class_emmc_init(oc);
@ -1498,6 +1512,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC3_ON;
amc->i2c_init = fuji_bmc_i2c_init;
amc->uart_default = ASPEED_DEV_UART1;
mc->auto_create_sdcard = true;
mc->default_ram_size = FUJI_BMC_RAM_SIZE;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1518,6 +1533,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = bletchley_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
aspeed_machine_class_init_cpus_defaults(mc);
}
@ -1559,6 +1575,7 @@ static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC3_ON;
amc->i2c_init = fby35_i2c_init;
mc->auto_create_sdcard = true;
/* FIXME: Replace this macro with something more general */
mc->default_ram_size = FUJI_BMC_RAM_SIZE;
aspeed_machine_class_init_cpus_defaults(mc);
@ -1669,6 +1686,7 @@ static void aspeed_machine_ast2700_evb_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
amc->uart_default = ASPEED_DEV_UART12;
amc->i2c_init = ast2700_evb_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
}
@ -1689,6 +1707,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
};
@ -1708,6 +1727,7 @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = qcom_dc_scm_firework_i2c_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
aspeed_machine_class_init_cpus_defaults(mc);
};

1
hw/arm/bananapi_m2u.c
View file

@ -141,6 +141,7 @@ static void bpim2u_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_ram_id = "bpim2u.ram";
mc->auto_create_sdcard = true;
}
DEFINE_MACHINE("bpim2u", bpim2u_machine_init)

1
hw/arm/cubieboard.c
View file

@ -122,6 +122,7 @@ static void cubieboard_machine_init(MachineClass *mc)
mc->units_per_default_bus = 1;
mc->ignore_memory_transaction_failures = true;
mc->default_ram_id = "cubieboard.ram";
mc->auto_create_sdcard = true;
}
DEFINE_MACHINE("cubieboard", cubieboard_machine_init)

2
hw/arm/exynos4_boards.c
View file

@ -165,6 +165,7 @@ static void nuri_class_init(ObjectClass *oc, void *data)
mc->min_cpus = EXYNOS4210_NCPUS;
mc->default_cpus = EXYNOS4210_NCPUS;
mc->ignore_memory_transaction_failures = true;
mc->auto_create_sdcard = true;
}
static const TypeInfo nuri_type = {
@ -184,6 +185,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *data)
mc->min_cpus = EXYNOS4210_NCPUS;
mc->default_cpus = EXYNOS4210_NCPUS;
mc->ignore_memory_transaction_failures = true;
mc->auto_create_sdcard = true;
}
static const TypeInfo smdkc210_type = {

1
hw/arm/fby35.c
View file

@ -170,6 +170,7 @@ static void fby35_class_init(ObjectClass *oc, void *data)
mc->init = fby35_init;
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->auto_create_sdcard = true;
mc->min_cpus = mc->max_cpus = mc->default_cpus = 3;
object_class_property_add_bool(oc, "execute-in-place",

1
hw/arm/imx25_pdk.c
View file

@ -147,6 +147,7 @@ static void imx25_pdk_machine_init(MachineClass *mc)
mc->init = imx25_pdk_init;
mc->ignore_memory_transaction_failures = true;
mc->default_ram_id = "imx25.ram";
mc->auto_create_sdcard = true;
}
DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init)

1
hw/arm/integratorcp.c
View file

@ -688,6 +688,7 @@ static void integratorcp_machine_init(MachineClass *mc)
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
mc->default_ram_id = "integrator.ram";
mc->auto_create_sdcard = true;
machine_add_audiodev_property(mc);
}

1
hw/arm/mcimx6ul-evk.c
View file

@ -74,5 +74,6 @@ static void mcimx6ul_evk_machine_init(MachineClass *mc)
mc->init = mcimx6ul_evk_init;
mc->max_cpus = FSL_IMX6UL_NUM_CPUS;
mc->default_ram_id = "mcimx6ul-evk.ram";
mc->auto_create_sdcard = true;
}
DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)

1
hw/arm/mcimx7d-sabre.c
View file

@ -74,5 +74,6 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc)
mc->init = mcimx7d_sabre_init;
mc->max_cpus = FSL_IMX7_NUM_CPUS;
mc->default_ram_id = "mcimx7d-sabre.ram";
mc->auto_create_sdcard = true;
}
DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init)

5
hw/arm/npcm7xx_boards.c
View file

@ -481,6 +481,7 @@ static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex-A9)";
mc->init = npcm750_evb_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
};
@ -493,6 +494,7 @@ static void gsj_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "Quanta GSJ (Cortex-A9)";
mc->init = quanta_gsj_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 512 * MiB;
};
@ -505,6 +507,7 @@ static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "Quanta GBS (Cortex-A9)";
mc->init = quanta_gbs_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
}
@ -517,6 +520,7 @@ static void kudo_bmc_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "Kudo BMC (Cortex-A9)";
mc->init = kudo_bmc_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
};
@ -529,6 +533,7 @@ static void mori_bmc_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "Mori BMC (Cortex-A9)";
mc->init = mori_bmc_init;
mc->auto_create_sdcard = true;
mc->default_ram_size = 1 * GiB;
}

2
hw/arm/omap_sx1.c
View file

@ -216,6 +216,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
mc->default_ram_size = SDRAM_SIZE;
mc->default_ram_id = "omap1.dram";
mc->auto_create_sdcard = true;
}
static const TypeInfo sx1_machine_v2_type = {
@ -234,6 +235,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t");
mc->default_ram_size = SDRAM_SIZE;
mc->default_ram_id = "omap1.dram";
mc->auto_create_sdcard = true;
}
static const TypeInfo sx1_machine_v1_type = {

1
hw/arm/orangepi.c
View file

@ -121,6 +121,7 @@ static void orangepi_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_ram_id = "orangepi.ram";
mc->auto_create_sdcard = true;
}
DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)

5
hw/arm/raspi.c
View file

@ -342,6 +342,7 @@ static void raspi0_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
mc->auto_create_sdcard = true;
rmc->board_rev = 0x920092; /* Revision 1.2 */
raspi_machine_class_init(mc, rmc->board_rev);
};
@ -351,6 +352,7 @@ static void raspi1ap_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
mc->auto_create_sdcard = true;
rmc->board_rev = 0x900021; /* Revision 1.1 */
raspi_machine_class_init(mc, rmc->board_rev);
};
@ -360,6 +362,7 @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
mc->auto_create_sdcard = true;
rmc->board_rev = 0xa21041;
raspi_machine_class_init(mc, rmc->board_rev);
};
@ -370,6 +373,7 @@ static void raspi3ap_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
mc->auto_create_sdcard = true;
rmc->board_rev = 0x9020e0; /* Revision 1.0 */
raspi_machine_class_init(mc, rmc->board_rev);
};
@ -379,6 +383,7 @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
RaspiBaseMachineClass *rmc = RASPI_BASE_MACHINE_CLASS(oc);
mc->auto_create_sdcard = true;
rmc->board_rev = 0xa02082;
raspi_machine_class_init(mc, rmc->board_rev);
};

1
hw/arm/raspi4b.c
View file

@ -118,6 +118,7 @@ static void raspi4b_machine_class_init(ObjectClass *oc, void *data)
rmc->board_rev = 0xb03115; /* Revision 1.5, 2 Gb RAM */
#endif
raspi_machine_class_common_init(mc, rmc->board_rev);
mc->auto_create_sdcard = true;
mc->init = raspi4b_machine_init;
}

4
hw/arm/realview.c
View file

@ -415,6 +415,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data)
mc->block_default_type = IF_SCSI;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
mc->auto_create_sdcard = true;
machine_add_audiodev_property(mc);
}
@ -435,6 +436,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)
mc->max_cpus = 4;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore");
mc->auto_create_sdcard = true;
machine_add_audiodev_property(mc);
}
@ -453,6 +455,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)
mc->init = realview_pb_a8_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8");
mc->auto_create_sdcard = true;
machine_add_audiodev_property(mc);
}
@ -472,6 +475,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)
mc->max_cpus = 4;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
mc->auto_create_sdcard = true;
machine_add_audiodev_property(mc);
}

1
hw/arm/sabrelite.c
View file

@ -110,6 +110,7 @@ static void sabrelite_machine_init(MachineClass *mc)
mc->max_cpus = FSL_IMX6_NUM_CPUS;
mc->ignore_memory_transaction_failures = true;
mc->default_ram_id = "sabrelite.ram";
mc->auto_create_sdcard = true;
}
DEFINE_MACHINE("sabrelite", sabrelite_machine_init)

1
hw/arm/stellaris.c
View file

@ -1441,6 +1441,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)
mc->init = lm3s6965evb_init;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
mc->auto_create_sdcard = true;
}
static const TypeInfo lm3s6965evb_type = {

2
hw/arm/versatilepb.c
View file

@ -419,6 +419,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data)
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
mc->default_ram_id = "versatile.ram";
mc->auto_create_sdcard = true;
machine_add_audiodev_property(mc);
}
@ -439,6 +440,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data)
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
mc->default_ram_id = "versatile.ram";
mc->auto_create_sdcard = true;
machine_add_audiodev_property(mc);
}

2
hw/arm/vexpress.c
View file

@ -803,6 +803,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, void *data)
mc->desc = "ARM Versatile Express for Cortex-A9";
mc->valid_cpu_types = valid_cpu_types;
mc->auto_create_sdcard = true;
vmc->daughterboard = &a9_daughterboard;
}
@ -818,6 +819,7 @@ static void vexpress_a15_class_init(ObjectClass *oc, void *data)
mc->desc = "ARM Versatile Express for Cortex-A15";
mc->valid_cpu_types = valid_cpu_types;
mc->auto_create_sdcard = true;
vmc->daughterboard = &a15_daughterboard;

1
hw/arm/xilinx_zynq.c
View file

@ -463,7 +463,6 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data)
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
mc->init = zynq_init;
mc->max_cpus = ZYNQ_MAX_CPUS;
mc->no_sdcard = 1;
mc->ignore_memory_transaction_failures = true;
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_id = "zynq.ext_ram";

1
hw/arm/xlnx-versal-virt.c
View file

@ -818,6 +818,7 @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data)
mc->max_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
mc->default_cpus = XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS;
mc->no_cdrom = true;
mc->auto_create_sdcard = true;
mc->default_ram_id = "ddr";
object_class_property_add_str(oc, "ospi-flash", versal_get_ospi_model,
versal_set_ospi_model);

1
hw/arm/xlnx-zcu102.c
View file

@ -280,6 +280,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
mc->default_ram_id = "ddr-ram";
mc->auto_create_sdcard = true;
machine_add_audiodev_property(mc);
object_class_property_add_bool(oc, "secure", zcu102_get_secure,

38
hw/arm/xlnx-zynqmp.c
View file

@ -689,16 +689,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
* - SDIO Specification Version 3.0
* - eMMC Specification Version 4.51
*/
if (!object_property_set_uint(sdhci, "sd-spec-version", 3, errp)) {
return;
}
if (!object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
errp)) {
return;
}
if (!object_property_set_uint(sdhci, "uhs", UHS_I, errp)) {
return;
}
object_property_set_uint(sdhci, "sd-spec-version", 3, &error_abort);
object_property_set_uint(sdhci, "capareg", SDHCI_CAPABILITIES,
&error_abort);
object_property_set_uint(sdhci, "uhs", UHS_I, &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(sdhci), errp)) {
return;
}
@ -763,14 +757,10 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
xlnx_zynqmp_create_unimp_mmio(s);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
errp)) {
return;
}
if (!object_property_set_link(OBJECT(&s->gdma[i]), "dma",
OBJECT(system_memory), errp)) {
return;
}
object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
&error_abort);
object_property_set_link(OBJECT(&s->gdma[i]), "dma",
OBJECT(system_memory), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gdma[i]), errp)) {
return;
}
@ -811,10 +801,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->qspi_dma), 0,
qdev_get_gpio_in(DEVICE(&s->qspi_irq_orgate), 0));
if (!object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
OBJECT(&s->qspi_dma), errp)) {
return;
}
object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma",
OBJECT(&s->qspi_dma), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->qspi), errp)) {
return;
}
@ -833,10 +821,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
}
for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
OBJECT(system_memory), errp)) {
return;
}
object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
OBJECT(system_memory), &error_abort);
qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);

26
hw/char/xilinx_uartlite.c
View file

@ -24,6 +24,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "hw/char/xilinx_uartlite.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
@ -57,6 +58,7 @@
struct XilinxUARTLite {
SysBusDevice parent_obj;
EndianMode model_endianness;
MemoryRegion mmio;
CharBackend chr;
qemu_irq irq;
@ -166,17 +168,21 @@ uart_write(void *opaque, hwaddr addr,
uart_update_irq(s);
}
static const MemoryRegionOps uart_ops = {
static const MemoryRegionOps uart_ops[2] = {
[0 ... 1] = {
.read = uart_read,
.write = uart_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 4
}
.max_access_size = 4,
},
},
[0].endianness = DEVICE_LITTLE_ENDIAN,
[1].endianness = DEVICE_BIG_ENDIAN,
};
static const Property xilinx_uartlite_properties[] = {
DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XilinxUARTLite, model_endianness),
DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr),
};
@ -214,6 +220,15 @@ static void xilinx_uartlite_realize(DeviceState *dev, Error **errp)
{
XilinxUARTLite *s = XILINX_UARTLITE(dev);
if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
error_setg(errp, TYPE_XILINX_UARTLITE " property 'endianness'"
" must be set to 'big' or 'little'");
return;
}
memory_region_init_io(&s->mmio, OBJECT(dev),
&uart_ops[s->model_endianness == ENDIAN_MODE_BIG],
s, "xlnx.xps-uartlite", R_MAX * 4);
qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
uart_event, NULL, s, NULL, true);
}
@ -223,9 +238,6 @@ static void xilinx_uartlite_init(Object *obj)
XilinxUARTLite *s = XILINX_UARTLITE(obj);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
memory_region_init_io(&s->mmio, obj, &uart_ops, s,
"xlnx.xps-uartlite", R_MAX * 4);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
}

7
hw/core/machine-smp.c
View file

@ -321,6 +321,13 @@ bool machine_parse_smp_cache(MachineState *ms,
return false;
}
if (props->topology == CPU_TOPOLOGY_LEVEL_THREAD) {
error_setg(errp,
"%s level cache not supported by this machine",
CpuTopologyLevel_str(props->topology));
return false;
}
if (!machine_check_topo_support(ms, props->topology, errp)) {
return false;
}

1
hw/core/null-machine.c
View file

@ -53,7 +53,6 @@ static void machine_none_machine_init(MachineClass *mc)
mc->no_parallel = 1;
mc->no_floppy = 1;
mc->no_cdrom = 1;
mc->no_sdcard = 1;
}
DEFINE_MACHINE("none", machine_none_machine_init)

11
hw/core/qdev-properties-system.c
View file

@ -1283,3 +1283,14 @@ const PropertyInfo qdev_prop_iothread_vq_mapping_list = {
.set = set_iothread_vq_mapping_list,
.release = release_iothread_vq_mapping_list,
};
/* --- Endian modes */
const PropertyInfo qdev_prop_endian_mode = {
.name = "EndianMode",
.description = "Endian mode, big/little/unspecified",
.enum_table = &EndianMode_lookup,
.get = qdev_propinfo_get_enum,
.set = qdev_propinfo_set_enum,
.set_default_value = qdev_propinfo_set_default_value_enum,
};

54
hw/core/sysbus.c
View file

@ -19,7 +19,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "monitor/monitor.h"
#include "exec/address-spaces.h"
@ -80,13 +79,6 @@ static void system_bus_class_init(ObjectClass *klass, void *data)
k->get_fw_dev_path = sysbus_get_fw_dev_path;
}
static const TypeInfo system_bus_info = {
.name = TYPE_SYSTEM_BUS,
.parent = TYPE_BUS,
.instance_size = sizeof(BusState),
.class_init = system_bus_class_init,
};
/* Check whether an IRQ source exists */
bool sysbus_has_irq(SysBusDevice *dev, int n)
{
@ -306,15 +298,6 @@ static void sysbus_device_class_init(ObjectClass *klass, void *data)
k->user_creatable = false;
}
static const TypeInfo sysbus_device_type_info = {
.name = TYPE_SYS_BUS_DEVICE,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SysBusDevice),
.abstract = true,
.class_size = sizeof(SysBusDeviceClass),
.class_init = sysbus_device_class_init,
};
static BusState *main_system_bus;
static void main_system_bus_create(void)
@ -323,8 +306,8 @@ static void main_system_bus_create(void)
* assign main_system_bus before qbus_init()
* in order to make "if (bus != sysbus_get_default())" work
*/
main_system_bus = g_malloc0(system_bus_info.instance_size);
qbus_init(main_system_bus, system_bus_info.instance_size,
main_system_bus = g_new0(BusState, 1);
qbus_init(main_system_bus, sizeof(BusState),
TYPE_SYSTEM_BUS, NULL, "main-system-bus");
OBJECT(main_system_bus)->free = g_free;
}
@ -337,10 +320,35 @@ BusState *sysbus_get_default(void)
return main_system_bus;
}
static void sysbus_register_types(void)
static void dynamic_sysbus_device_class_init(ObjectClass *klass, void *data)
{
type_register_static(&system_bus_info);
type_register_static(&sysbus_device_type_info);
DeviceClass *k = DEVICE_CLASS(klass);
k->user_creatable = true;
k->hotpluggable = false;
}
type_init(sysbus_register_types)
static const TypeInfo sysbus_types[] = {
{
.name = TYPE_SYSTEM_BUS,
.parent = TYPE_BUS,
.instance_size = sizeof(BusState),
.class_init = system_bus_class_init,
},
{
.name = TYPE_SYS_BUS_DEVICE,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SysBusDevice),
.abstract = true,
.class_size = sizeof(SysBusDeviceClass),
.class_init = sysbus_device_class_init,
},
{
.name = TYPE_DYNAMIC_SYS_BUS_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
.class_init = dynamic_sysbus_device_class_init,
.abstract = true,
}
};
DEFINE_TYPES(sysbus_types)

3
hw/display/ramfb-standalone.c
View file

@ -72,13 +72,12 @@ static void ramfb_class_initfn(ObjectClass *klass, void *data)
dc->vmsd = &ramfb_dev_vmstate;
dc->realize = ramfb_realizefn;
dc->desc = "ram framebuffer standalone device";
dc->user_creatable = true;
device_class_set_props(dc, ramfb_properties);
}
static const TypeInfo ramfb_info = {
.name = TYPE_RAMFB_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
.parent = TYPE_DYNAMIC_SYS_BUS_DEVICE,
.instance_size = sizeof(RAMFBStandaloneState),
.class_init = ramfb_class_initfn,
};

2
hw/i2c/allwinner-i2c.c
View file

@ -407,7 +407,7 @@ static const MemoryRegionOps allwinner_i2c_ops = {
.write = allwinner_i2c_write,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription allwinner_i2c_vmstate = {

2
hw/i386/amd_iommu.c
View file

@ -1687,8 +1687,6 @@ static void amdvi_sysbus_class_init(ObjectClass *klass, void *data)
dc->hotpluggable = false;
dc_class->realize = amdvi_sysbus_realize;
dc_class->int_remap = amdvi_int_remap;
/* Supported by the pc-q35-* machine types */
dc->user_creatable = true;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->desc = "AMD IOMMU (AMD-Vi) DMA Remapping device";
device_class_set_props(dc, amdvi_properties);

2
hw/i386/intel_iommu.c
View file

@ -4871,8 +4871,6 @@ static void vtd_class_init(ObjectClass *klass, void *data)
dc->hotpluggable = false;
x86_class->realize = vtd_realize;
x86_class->int_remap = vtd_int_remap;
/* Supported by the pc-q35-* machine types */
dc->user_creatable = true;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
dc->desc = "Intel IOMMU (VT-d) DMA Remapping device";
}

2
hw/i386/x86-iommu.c
View file

@ -146,7 +146,7 @@ bool x86_iommu_ir_supported(X86IOMMUState *s)
static const TypeInfo x86_iommu_info = {
.name = TYPE_X86_IOMMU_DEVICE,
.parent = TYPE_SYS_BUS_DEVICE,
.parent = TYPE_DYNAMIC_SYS_BUS_DEVICE,
.instance_size = sizeof(X86IOMMUState),
.class_init = x86_iommu_class_init,
.class_size = sizeof(X86IOMMUClass),

2
hw/intc/allwinner-a10-pic.c
View file

@ -135,7 +135,7 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps aw_a10_pic_ops = {
.read = aw_a10_pic_read,
.write = aw_a10_pic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription vmstate_aw_a10_pic = {

3
hw/intc/apic.c
View file

@ -350,9 +350,8 @@ static int apic_set_base(APICCommonState *s, uint64_t val)
return -1;
}
s->apicbase = (val & 0xfffff000) |
s->apicbase = (val & MSR_IA32_APICBASE_BASE) |
(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
/* if disabled, cannot be enabled again */
if (!(val & MSR_IA32_APICBASE_ENABLE)) {
s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
cpu_clear_apic_feature(&s->cpu->env);

45
hw/intc/xilinx_intc.c
View file

@ -3,6 +3,9 @@
*
* Copyright (c) 2009 Edgar E. Iglesias.
*
* https://docs.amd.com/v/u/en-US/xps_intc
* DS572: LogiCORE IP XPS Interrupt Controller (v2.01a)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@ -23,10 +26,12 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "qom/object.h"
#define D(x)
@ -49,6 +54,7 @@ struct XpsIntc
{
SysBusDevice parent_obj;
EndianMode model_endianness;
MemoryRegion mmio;
qemu_irq parent_irq;
@ -140,18 +146,28 @@ static void pic_write(void *opaque, hwaddr addr,
update_irq(p);
}
static const MemoryRegionOps pic_ops = {
static const MemoryRegionOps pic_ops[2] = {
[0 ... 1] = {
.read = pic_read,
.write = pic_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
.valid = {
/*
* All XPS INTC registers are accessed through the PLB interface.
* The base address for these registers is provided by the
* configuration parameter, C_BASEADDR. Each register is 32 bits
* although some bits may be unused and is accessed on a 4-byte
* boundary offset from the base address.
*/
.min_access_size = 4,
.max_access_size = 4
}
.max_access_size = 4,
},
},
[0].endianness = DEVICE_LITTLE_ENDIAN,
[1].endianness = DEVICE_BIG_ENDIAN,
};
static void irq_handler(void *opaque, int irq, int level)
@ -174,13 +190,27 @@ static void xilinx_intc_init(Object *obj)
qdev_init_gpio_in(DEVICE(obj), irq_handler, 32);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &p->parent_irq);
memory_region_init_io(&p->mmio, obj, &pic_ops, p, "xlnx.xps-intc",
R_MAX * 4);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio);
}
static void xilinx_intc_realize(DeviceState *dev, Error **errp)
{
XpsIntc *p = XILINX_INTC(dev);
if (p->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
error_setg(errp, TYPE_XILINX_INTC " property 'endianness'"
" must be set to 'big' or 'little'");
return;
}
memory_region_init_io(&p->mmio, OBJECT(dev),
&pic_ops[p->model_endianness == ENDIAN_MODE_BIG],
p, "xlnx.xps-intc",
R_MAX * 4);
}
static const Property xilinx_intc_properties[] = {
DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XpsIntc, model_endianness),
DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0),
};
@ -188,6 +218,7 @@ static void xilinx_intc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = xilinx_intc_realize;
device_class_set_props(dc, xilinx_intc_properties);
}

2
hw/isa/vt82c686.c
View file

@ -224,7 +224,7 @@ static void via_pm_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
ViaPMInitInfo *info = data;
const ViaPMInitInfo *info = data;
k->realize = via_pm_realize;
k->config_write = pm_write_config;

5
hw/microblaze/petalogix_ml605_mmu.c
View file

@ -80,6 +80,8 @@ petalogix_ml605_init(MachineState *machine)
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG
: ENDIAN_MODE_LITTLE;
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
@ -111,6 +113,7 @@ petalogix_ml605_init(MachineState *machine)
dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_enum(dev, "endianness", endianness);
qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
@ -126,6 +129,7 @@ petalogix_ml605_init(MachineState *machine)
/* 2 timers at irq 2 @ 100 Mhz. */
dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_enum(dev, "endianness", endianness);
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -173,6 +177,7 @@ petalogix_ml605_init(MachineState *machine)
SSIBus *spi;
dev = qdev_new("xlnx.xps-spi");
qdev_prop_set_enum(dev, "endianness", endianness);
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
busdev = SYS_BUS_DEVICE(dev);
sysbus_realize_and_unref(busdev, &error_fatal);

6
hw/microblaze/petalogix_s3adsp1800_mmu.c
View file

@ -71,6 +71,8 @@ petalogix_s3adsp1800_init(MachineState *machine)
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
MemoryRegion *sysmem = get_system_memory();
EndianMode endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG
: ENDIAN_MODE_LITTLE;
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_str(OBJECT(cpu), "version", "7.10.d", &error_abort);
@ -95,6 +97,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_enum(dev, "endianness", endianness);
qdev_prop_set_uint32(dev, "kind-of-intr",
1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -106,6 +109,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
}
dev = qdev_new(TYPE_XILINX_UARTLITE);
qdev_prop_set_enum(dev, "endianness", endianness);
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
@ -113,6 +117,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
/* 2 timers at irq 2 @ 62 Mhz. */
dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_enum(dev, "endianness", endianness);
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -120,6 +125,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
dev = qdev_new("xlnx.xps-ethernetlite");
qdev_prop_set_enum(dev, "endianness", endianness);
qemu_configure_nic_device(dev, true, NULL);
qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
qdev_prop_set_uint32(dev, "rx-ping-pong", 0);

6
hw/mips/boston.c
View file

@ -220,7 +220,7 @@ static void boston_lcd_write(void *opaque, hwaddr addr,
static const MemoryRegionOps boston_lcd_ops = {
.read = boston_lcd_read,
.write = boston_lcd_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
@ -299,7 +299,7 @@ static void boston_platreg_write(void *opaque, hwaddr addr,
static const MemoryRegionOps boston_platreg_ops = {
.read = boston_platreg_read,
.write = boston_platreg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void mips_boston_instance_init(Object *obj)
@ -758,7 +758,7 @@ static void boston_mach_init(MachineState *machine)
s->uart = serial_mm_init(sys_mem, boston_memmap[BOSTON_UART].base, 2,
get_cps_irq(&s->cps, 3), 10000000,
serial_hd(0), DEVICE_NATIVE_ENDIAN);
serial_hd(0), DEVICE_LITTLE_ENDIAN);
lcd = g_new(MemoryRegion, 1);
memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);

4
hw/mips/loongson3_virt.c
View file

@ -144,7 +144,7 @@ static void loongson3_pm_write(void *opaque, hwaddr addr,
static const MemoryRegionOps loongson3_pm_ops = {
.read = loongson3_pm_read,
.write = loongson3_pm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 1,
.max_access_size = 1
@ -560,7 +560,7 @@ static void mips_loongson3_virt_init(MachineState *machine)
serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0),
DEVICE_NATIVE_ENDIAN);
DEVICE_LITTLE_ENDIAN);
sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
qdev_get_gpio_in(liointc, RTC_IRQ));

2
hw/misc/allwinner-a10-ccm.c
View file

@ -147,7 +147,7 @@ static void allwinner_a10_ccm_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_a10_ccm_ops = {
.read = allwinner_a10_ccm_read,
.write = allwinner_a10_ccm_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/misc/allwinner-a10-dramc.c
View file

@ -114,7 +114,7 @@ static void allwinner_a10_dramc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_a10_dramc_ops = {
.read = allwinner_a10_dramc_read,
.write = allwinner_a10_dramc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/misc/allwinner-cpucfg.c
View file

@ -217,7 +217,7 @@ static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_cpucfg_ops = {
.read = allwinner_cpucfg_read,
.write = allwinner_cpucfg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/misc/allwinner-h3-ccu.c
View file

@ -155,7 +155,7 @@ static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_h3_ccu_ops = {
.read = allwinner_h3_ccu_read,
.write = allwinner_h3_ccu_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

6
hw/misc/allwinner-h3-dramc.c
View file

@ -219,7 +219,7 @@ static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_h3_dramcom_ops = {
.read = allwinner_h3_dramcom_read,
.write = allwinner_h3_dramcom_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@ -230,7 +230,7 @@ static const MemoryRegionOps allwinner_h3_dramcom_ops = {
static const MemoryRegionOps allwinner_h3_dramctl_ops = {
.read = allwinner_h3_dramctl_read,
.write = allwinner_h3_dramctl_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@ -241,7 +241,7 @@ static const MemoryRegionOps allwinner_h3_dramctl_ops = {
static const MemoryRegionOps allwinner_h3_dramphy_ops = {
.read = allwinner_h3_dramphy_read,
.write = allwinner_h3_dramphy_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/misc/allwinner-h3-sysctrl.c
View file

@ -78,7 +78,7 @@ static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_h3_sysctrl_ops = {
.read = allwinner_h3_sysctrl_read,
.write = allwinner_h3_sysctrl_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/misc/allwinner-r40-ccu.c
View file

@ -129,7 +129,7 @@ static void allwinner_r40_ccu_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_r40_ccu_ops = {
.read = allwinner_r40_ccu_read,
.write = allwinner_r40_ccu_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

10
hw/misc/allwinner-r40-dramc.c
View file

@ -297,7 +297,7 @@ static void allwinner_r40_dramphy_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_r40_dramcom_ops = {
.read = allwinner_r40_dramcom_read,
.write = allwinner_r40_dramcom_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@ -308,7 +308,7 @@ static const MemoryRegionOps allwinner_r40_dramcom_ops = {
static const MemoryRegionOps allwinner_r40_dramctl_ops = {
.read = allwinner_r40_dramctl_read,
.write = allwinner_r40_dramctl_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@ -319,7 +319,7 @@ static const MemoryRegionOps allwinner_r40_dramctl_ops = {
static const MemoryRegionOps allwinner_r40_dramphy_ops = {
.read = allwinner_r40_dramphy_read,
.write = allwinner_r40_dramphy_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@ -358,7 +358,7 @@ static void allwinner_r40_detect_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_r40_detect_ops = {
.read = allwinner_r40_detect_read,
.write = allwinner_r40_detect_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@ -393,7 +393,7 @@ static uint64_t allwinner_r40_dualrank_detect_read(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_r40_dualrank_detect_ops = {
.read = allwinner_r40_dualrank_detect_read,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/misc/allwinner-sid.c
View file

@ -99,7 +99,7 @@ static void allwinner_sid_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_sid_ops = {
.read = allwinner_sid_read,
.write = allwinner_sid_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/misc/allwinner-sramc.c
View file

@ -104,7 +104,7 @@ static void allwinner_sramc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_sramc_ops = {
.read = allwinner_sramc_read,
.write = allwinner_sramc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/net/allwinner-sun8i-emac.c
View file

@ -784,7 +784,7 @@ static void allwinner_sun8i_emac_set_link(NetClientState *nc)
static const MemoryRegionOps allwinner_sun8i_emac_mem_ops = {
.read = allwinner_sun8i_emac_read,
.write = allwinner_sun8i_emac_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/net/allwinner_emac.c
View file

@ -421,7 +421,7 @@ static void aw_emac_set_link(NetClientState *nc)
static const MemoryRegionOps aw_emac_mem_ops = {
.read = aw_emac_read,
.write = aw_emac_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

4
hw/net/fsl_etsec/etsec.c
View file

@ -425,14 +425,12 @@ static void etsec_class_init(ObjectClass *klass, void *data)
dc->realize = etsec_realize;
device_class_set_legacy_reset(dc, etsec_reset);
device_class_set_props(dc, etsec_properties);
/* Supported by ppce500 machine */
dc->user_creatable = true;
}
static const TypeInfo etsec_types[] = {
{
.name = TYPE_ETSEC_COMMON,
.parent = TYPE_SYS_BUS_DEVICE,
.parent = TYPE_DYNAMIC_SYS_BUS_DEVICE,
.instance_size = sizeof(eTSEC),
.class_init = etsec_class_init,
.instance_init = etsec_instance_init,

9
hw/net/smc91c111.c
View file

@ -182,6 +182,15 @@ static void smc91c111_pop_rx_fifo(smc91c111_state *s)
{
int i;
if (s->rx_fifo_len == 0) {
/*
* The datasheet doesn't document what the behaviour is if the
* guest tries to pop an empty RX FIFO, and there's no obvious
* error status register to report it. Just ignore the attempt.
*/
return;
}
s->rx_fifo_len--;
if (s->rx_fifo_len) {
for (i = 0; i < s->rx_fifo_len; i++)

29
hw/net/xilinx_ethlite.c
View file

@ -34,6 +34,7 @@
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "hw/misc/unimp.h"
#include "net/net.h"
#include "trace.h"
@ -85,6 +86,7 @@ struct XlnxXpsEthLite
{
SysBusDevice parent_obj;
EndianMode model_endianness;
MemoryRegion container;
qemu_irq irq;
NICState *nic;
@ -183,10 +185,10 @@ static void port_tx_write(void *opaque, hwaddr addr, uint64_t value,
}
}
static const MemoryRegionOps eth_porttx_ops = {
static const MemoryRegionOps eth_porttx_ops[2] = {
[0 ... 1] = {
.read = port_tx_read,
.write = port_tx_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
@ -195,6 +197,9 @@ static const MemoryRegionOps eth_porttx_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
},
[0].endianness = DEVICE_LITTLE_ENDIAN,
[1].endianness = DEVICE_BIG_ENDIAN,
};
static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size)
@ -232,10 +237,10 @@ static void port_rx_write(void *opaque, hwaddr addr, uint64_t value,
}
}
static const MemoryRegionOps eth_portrx_ops = {
static const MemoryRegionOps eth_portrx_ops[2] = {
[0 ... 1] = {
.read = port_rx_read,
.write = port_rx_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
@ -244,6 +249,9 @@ static const MemoryRegionOps eth_portrx_ops = {
.min_access_size = 4,
.max_access_size = 4,
},
},
[0].endianness = DEVICE_LITTLE_ENDIAN,
[1].endianness = DEVICE_BIG_ENDIAN,
};
static bool eth_can_rx(NetClientState *nc)
@ -300,6 +308,14 @@ static NetClientInfo net_xilinx_ethlite_info = {
static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
{
XlnxXpsEthLite *s = XILINX_ETHLITE(dev);
unsigned ops_index;
if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
error_setg(errp, TYPE_XILINX_ETHLITE " property 'endianness'"
" must be set to 'big' or 'little'");
return;
}
ops_index = s->model_endianness == ENDIAN_MODE_BIG ? 1 : 0;
memory_region_init(&s->container, OBJECT(dev),
"xlnx.xps-ethernetlite", 0x2000);
@ -328,7 +344,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
BUFSZ_MAX, &error_abort);
memory_region_add_subregion(&s->container, 0x0800 * i, &s->port[i].txbuf);
memory_region_init_io(&s->port[i].txio, OBJECT(dev),
&eth_porttx_ops, s,
&eth_porttx_ops[ops_index], s,
i ? "ethlite.tx[1]io" : "ethlite.tx[0]io",
4 * TX_MAX);
memory_region_add_subregion(&s->container, i ? A_TX_BASE1 : A_TX_BASE0,
@ -340,7 +356,7 @@ static void xilinx_ethlite_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->container, 0x1000 + 0x0800 * i,
&s->port[i].rxbuf);
memory_region_init_io(&s->port[i].rxio, OBJECT(dev),
&eth_portrx_ops, s,
&eth_portrx_ops[ops_index], s,
i ? "ethlite.rx[1]io" : "ethlite.rx[0]io",
4 * RX_MAX);
memory_region_add_subregion(&s->container, i ? A_RX_BASE1 : A_RX_BASE0,
@ -363,6 +379,7 @@ static void xilinx_ethlite_init(Object *obj)
}
static const Property xilinx_ethlite_properties[] = {
DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XlnxXpsEthLite, model_endianness),
DEFINE_PROP_UINT32("tx-ping-pong", XlnxXpsEthLite, c_tx_pingpong, 1),
DEFINE_PROP_UINT32("rx-ping-pong", XlnxXpsEthLite, c_rx_pingpong, 1),
DEFINE_NIC_PROPERTIES(XlnxXpsEthLite, conf),

4
hw/pci-host/versatile.c
View file

@ -246,7 +246,7 @@ static uint64_t pci_vpb_reg_read(void *opaque, hwaddr addr,
static const MemoryRegionOps pci_vpb_reg_ops = {
.read = pci_vpb_reg_read,
.write = pci_vpb_reg_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
@ -312,7 +312,7 @@ static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr,
static const MemoryRegionOps pci_vpb_config_ops = {
.read = pci_vpb_config_read,
.write = pci_vpb_config_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int pci_vpb_map_irq(PCIDevice *d, int irq_num)

2
hw/ppc/virtex_ml507.c
View file

@ -217,6 +217,7 @@ static void virtex_init(MachineState *machine)
cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT);
dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_BIG);
qdev_prop_set_uint32(dev, "kind-of-intr", 0);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
@ -230,6 +231,7 @@ static void virtex_init(MachineState *machine)
/* 2 timers at irq 2 @ 62 Mhz. */
dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_BIG);
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

5
hw/riscv/microblaze-v-generic.c
View file

@ -79,6 +79,7 @@ static void mb_v_generic_init(MachineState *machine)
memory_region_add_subregion(sysmem, ddr_base, phys_ram);
dev = qdev_new("xlnx.xps-intc");
qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint32(dev, "kind-of-intr",
1 << UARTLITE_IRQ);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -91,6 +92,7 @@ static void mb_v_generic_init(MachineState *machine)
/* Uartlite */
dev = qdev_new(TYPE_XILINX_UARTLITE);
qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_chr(dev, "chardev", serial_hd(0));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
@ -103,6 +105,7 @@ static void mb_v_generic_init(MachineState *machine)
/* 2 timers at irq 0 @ 100 Mhz. */
dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -111,6 +114,7 @@ static void mb_v_generic_init(MachineState *machine)
/* 2 timers at irq 3 @ 100 Mhz. */
dev = qdev_new("xlnx.xps-timer");
qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
@ -119,6 +123,7 @@ static void mb_v_generic_init(MachineState *machine)
/* Emaclite */
dev = qdev_new("xlnx.xps-ethernetlite");
qdev_prop_set_enum(dev, "endianness", ENDIAN_MODE_LITTLE);
qemu_configure_nic_device(dev, true, NULL);
qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
qdev_prop_set_uint32(dev, "rx-ping-pong", 0);

1
hw/riscv/microchip_pfsoc.c
View file

@ -650,6 +650,7 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
mc->default_cpus = mc->min_cpus;
mc->default_ram_id = "microchip.icicle.kit.ram";
mc->auto_create_sdcard = true;
/*
* Map 513 MiB high memory, the minimum required high memory size, because

1
hw/riscv/opentitan.c
View file

@ -28,6 +28,7 @@
#include "hw/riscv/boot.h"
#include "qemu/units.h"
#include "system/system.h"
#include "exec/address-spaces.h"
/*
* This version of the OpenTitan machine currently supports

1
hw/riscv/sifive_u.c
View file

@ -724,6 +724,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
mc->default_cpu_type = SIFIVE_U_CPU;
mc->default_cpus = mc->min_cpus;
mc->default_ram_id = "riscv.sifive.u.ram";
mc->auto_create_sdcard = true;
object_class_property_add_bool(oc, "start-in-flash",
sifive_u_machine_get_start_in_flash,

2
hw/rtc/allwinner-rtc.c
View file

@ -259,7 +259,7 @@ static void allwinner_rtc_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_rtc_ops = {
.read = allwinner_rtc_read,
.write = allwinner_rtc_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/rtc/m48t59-isa.c
View file

@ -129,7 +129,7 @@ static void m48txx_isa_class_init(ObjectClass *klass, void *data)
static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
{
M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
M48txxInfo *info = data;
const M48txxInfo *info = data;
u->info = *info;
}

2
hw/rtc/m48t59.c
View file

@ -639,7 +639,7 @@ static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
{
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
M48txxInfo *info = data;
const M48txxInfo *info = data;
u->info = *info;
}

3
hw/rx/rx-gdbsim.c
View file

@ -110,9 +110,6 @@ static void rx_gdbsim_init(MachineState *machine)
if (!kernel_filename) {
if (machine->firmware) {
rom_add_file_fixed(machine->firmware, RX62N_CFLASH_BASE, 0);
} else if (!qtest_enabled()) {
error_report("No bios or kernel specified");
exit(1);
}
}

1
hw/s390x/s390-virtio-ccw.c
View file

@ -817,7 +817,6 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data)
mc->no_cdrom = 1;
mc->no_floppy = 1;
mc->no_parallel = 1;
mc->no_sdcard = 1;
mc->max_cpus = S390_MAX_CPUS;
mc->has_hotpluggable_cpus = true;
mc->smp_props.books_supported = true;

2
hw/sd/allwinner-sdhost.c
View file

@ -761,7 +761,7 @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_sdhost_ops = {
.read = allwinner_sdhost_read,
.write = allwinner_sdhost_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

2
hw/sd/sdhci-internal.h
View file

@ -322,6 +322,6 @@ void sdhci_initfn(SDHCIState *s);
void sdhci_uninitfn(SDHCIState *s);
void sdhci_common_realize(SDHCIState *s, Error **errp);
void sdhci_common_unrealize(SDHCIState *s);
void sdhci_common_class_init(ObjectClass *klass, void *data);
void sdhci_common_class_init(ObjectClass *klass, const void *data);
#endif

2
hw/sd/sdhci.c
View file

@ -1542,7 +1542,7 @@ const VMStateDescription sdhci_vmstate = {
},
};
void sdhci_common_class_init(ObjectClass *klass, void *data)
void sdhci_common_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);

2
hw/sensor/emc141x.c
View file

@ -265,7 +265,7 @@ static void emc141x_initfn(Object *obj)
emc141x_set_temperature, NULL, NULL);
}
static void emc141x_class_init(ObjectClass *klass, void *data)
static void emc141x_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);

2
hw/sensor/isl_pmbus_vr.c
View file

@ -233,7 +233,7 @@ static void raa228000_init(Object *obj)
isl_pmbus_vr_add_props(obj, flags, 1);
}
static void isl_pmbus_vr_class_init(ObjectClass *klass, void *data,
static void isl_pmbus_vr_class_init(ObjectClass *klass, const void *data,
uint8_t pages)
{
PMBusDeviceClass *k = PMBUS_DEVICE_CLASS(klass);

2
hw/sensor/tmp421.c
View file

@ -68,7 +68,7 @@ struct TMP421State {
struct TMP421Class {
I2CSlaveClass parent_class;
DeviceInfo *dev;
const DeviceInfo *dev;
};
#define TYPE_TMP421 "tmp421-generic"

2
hw/ssi/allwinner-a10-spi.c
View file

@ -502,7 +502,7 @@ static const MemoryRegionOps allwinner_a10_spi_ops = {
.write = allwinner_a10_spi_write,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const VMStateDescription allwinner_a10_spi_vmstate = {

24
hw/ssi/xilinx_spi.c
View file

@ -25,6 +25,7 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
@ -32,6 +33,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "hw/ssi/ssi.h"
#include "qom/object.h"
@ -83,6 +85,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XilinxSPI, XILINX_SPI)
struct XilinxSPI {
SysBusDevice parent_obj;
EndianMode model_endianness;
MemoryRegion mmio;
qemu_irq irq;
@ -313,14 +316,17 @@ done:
xlx_spi_update_irq(s);
}
static const MemoryRegionOps spi_ops = {
static const MemoryRegionOps spi_ops[2] = {
[0 ... 1] = {
.read = spi_read,
.write = spi_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4
}
.max_access_size = 4,
},
},
[0].endianness = DEVICE_LITTLE_ENDIAN,
[1].endianness = DEVICE_BIG_ENDIAN,
};
static void xilinx_spi_realize(DeviceState *dev, Error **errp)
@ -329,6 +335,12 @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp)
XilinxSPI *s = XILINX_SPI(dev);
int i;
if (s->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
error_setg(errp, TYPE_XILINX_SPI " property 'endianness'"
" must be set to 'big' or 'little'");
return;
}
DB_PRINT("\n");
s->spi = ssi_create_bus(dev, "spi");
@ -339,7 +351,8 @@ static void xilinx_spi_realize(DeviceState *dev, Error **errp)
sysbus_init_irq(sbd, &s->cs_lines[i]);
}
memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
memory_region_init_io(&s->mmio, OBJECT(s),
&spi_ops[s->model_endianness == ENDIAN_MODE_BIG], s,
"xilinx-spi", R_MAX * 4);
sysbus_init_mmio(sbd, &s->mmio);
@ -362,6 +375,7 @@ static const VMStateDescription vmstate_xilinx_spi = {
};
static const Property xilinx_spi_properties[] = {
DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XilinxSPI, model_endianness),
DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
};

2
hw/timer/allwinner-a10-pit.c
View file

@ -185,7 +185,7 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps a10_pit_ops = {
.read = a10_pit_read,
.write = a10_pit_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static const Property a10_pit_properties[] = {

29
hw/timer/xilinx_timer.c
View file

@ -3,6 +3,9 @@
*
* Copyright (c) 2009 Edgar E. Iglesias.
*
* DS573: https://docs.amd.com/v/u/en-US/xps_timer
* LogiCORE IP XPS Timer/Counter (v1.02a)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
@ -23,10 +26,12 @@
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qom/object.h"
@ -69,6 +74,7 @@ struct XpsTimerState
{
SysBusDevice parent_obj;
EndianMode model_endianness;
MemoryRegion mmio;
qemu_irq irq;
uint8_t one_timer_only;
@ -189,18 +195,21 @@ timer_write(void *opaque, hwaddr addr,
timer_update_irq(t);
}
static const MemoryRegionOps timer_ops = {
static const MemoryRegionOps timer_ops[2] = {
[0 ... 1] = {
.read = timer_read,
.write = timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
.valid = {
.min_access_size = 4,
.max_access_size = 4
}
.max_access_size = 4,
},
},
[0].endianness = DEVICE_LITTLE_ENDIAN,
[1].endianness = DEVICE_BIG_ENDIAN,
};
static void timer_hit(void *opaque)
@ -220,6 +229,12 @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
XpsTimerState *t = XILINX_TIMER(dev);
unsigned int i;
if (t->model_endianness == ENDIAN_MODE_UNSPECIFIED) {
error_setg(errp, TYPE_XILINX_TIMER " property 'endianness'"
" must be set to 'big' or 'little'");
return;
}
/* Init all the ptimers. */
t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
for (i = 0; i < num_timers(t); i++) {
@ -233,8 +248,9 @@ static void xilinx_timer_realize(DeviceState *dev, Error **errp)
ptimer_transaction_commit(xt->ptimer);
}
memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
R_MAX * 4 * num_timers(t));
memory_region_init_io(&t->mmio, OBJECT(t),
&timer_ops[t->model_endianness == ENDIAN_MODE_BIG],
t, "xlnx.xps-timer", R_MAX * 4 * num_timers(t));
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
}
@ -247,6 +263,7 @@ static void xilinx_timer_init(Object *obj)
}
static const Property xilinx_timer_properties[] = {
DEFINE_PROP_ENDIAN_NODEFAULT("endianness", XpsTimerState, model_endianness),
DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000),
DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0),
};

3
hw/tpm/tpm_tis_sysbus.c
View file

@ -133,7 +133,6 @@ static void tpm_tis_sysbus_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_tpm_tis_sysbus;
tc->model = TPM_MODEL_TPM_TIS;
dc->realize = tpm_tis_sysbus_realizefn;
dc->user_creatable = true;
device_class_set_legacy_reset(dc, tpm_tis_sysbus_reset);
tc->request_completed = tpm_tis_sysbus_request_completed;
tc->get_version = tpm_tis_sysbus_get_tpm_version;
@ -142,7 +141,7 @@ static void tpm_tis_sysbus_class_init(ObjectClass *klass, void *data)
static const TypeInfo tpm_tis_sysbus_info = {
.name = TYPE_TPM_TIS_SYSBUS,
.parent = TYPE_SYS_BUS_DEVICE,
.parent = TYPE_DYNAMIC_SYS_BUS_DEVICE,
.instance_size = sizeof(TPMStateSysBus),
.instance_init = tpm_tis_sysbus_initfn,
.class_init = tpm_tis_sysbus_class_init,

2
hw/usb/hcd-ehci-pci.c
View file

@ -182,7 +182,7 @@ static void ehci_data_class_init(ObjectClass *klass, void *data)
{
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
EHCIPCIInfo *i = data;
const EHCIPCIInfo *i = data;
k->vendor_id = i->vendor_id;
k->device_id = i->device_id;

2
hw/usb/hcd-uhci.c
View file

@ -1289,7 +1289,7 @@ void uhci_data_class_init(ObjectClass *klass, void *data)
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
UHCIPCIDeviceClass *u = UHCI_CLASS(klass);
UHCIInfo *info = data;
const UHCIInfo *info = data;
k->realize = info->realize ? info->realize : usb_uhci_common_realize;
k->exit = info->unplug ? usb_uhci_exit : NULL;

6
hw/usb/xen-usb.c
View file

@ -755,10 +755,10 @@ static void usbback_portid_add(struct usbback_info *usbif, unsigned port,
qdict = qdict_new();
qdict_put_str(qdict, "driver", "usb-host");
tmp = g_strdup_printf("%s.0", usbif->xendev.qdev.id);
tmp = g_strdup_printf("%s.0", DEVICE(&usbif->xendev)->id);
qdict_put_str(qdict, "bus", tmp);
g_free(tmp);
tmp = g_strdup_printf("%s-%u", usbif->xendev.qdev.id, port);
tmp = g_strdup_printf("%s-%u", DEVICE(&usbif->xendev)->id, port);
qdict_put_str(qdict, "id", tmp);
g_free(tmp);
qdict_put_int(qdict, "port", port);
@ -1022,7 +1022,7 @@ static void usbback_alloc(struct XenLegacyDevice *xendev)
usbif = container_of(xendev, struct usbback_info, xendev);
usb_bus_new(&usbif->bus, sizeof(usbif->bus), &xen_usb_bus_ops,
DEVICE(&xendev->qdev));
DEVICE(xendev));
for (i = 0; i < USBBACK_MAXPORTS; i++) {
p = &(usbif->ports[i].port);
usb_register_port(&usbif->bus, p, usbif, i, &xen_usb_port_ops,

2
hw/vfio/amd-xgbe.c
View file

@ -41,8 +41,6 @@ static void vfio_amd_xgbe_class_init(ObjectClass *klass, void *data)
&vcxc->parent_realize);
dc->desc = "VFIO AMD XGBE";
dc->vmsd = &vfio_platform_amd_xgbe_vmstate;
/* Supported by TYPE_VIRT_MACHINE */
dc->user_creatable = true;
}
static const TypeInfo vfio_amd_xgbe_dev_info = {

2
hw/vfio/calxeda-xgmac.c
View file

@ -41,8 +41,6 @@ static void vfio_calxeda_xgmac_class_init(ObjectClass *klass, void *data)
&vcxc->parent_realize);
dc->desc = "VFIO Calxeda XGMAC";
dc->vmsd = &vfio_platform_calxeda_xgmac_vmstate;
/* Supported by TYPE_VIRT_MACHINE */
dc->user_creatable = true;
}
static const TypeInfo vfio_calxeda_xgmac_dev_info = {

4
hw/vfio/platform.c
View file

@ -672,13 +672,11 @@ static void vfio_platform_class_init(ObjectClass *klass, void *data)
dc->desc = "VFIO-based platform device assignment";
sbc->connect_irq_notifier = vfio_start_irqfd_injection;
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
/* Supported by TYPE_VIRT_MACHINE */
dc->user_creatable = true;
}
static const TypeInfo vfio_platform_dev_info = {
.name = TYPE_VFIO_PLATFORM,
.parent = TYPE_SYS_BUS_DEVICE,
.parent = TYPE_DYNAMIC_SYS_BUS_DEVICE,
.instance_size = sizeof(VFIOPlatformDevice),
.instance_init = vfio_platform_instance_init,
.class_init = vfio_platform_class_init,

2
hw/watchdog/allwinner-wdt.c
View file

@ -275,7 +275,7 @@ static void allwinner_wdt_write(void *opaque, hwaddr offset,
static const MemoryRegionOps allwinner_wdt_ops = {
.read = allwinner_wdt_read,
.write = allwinner_wdt_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,

9
hw/xen/xen-legacy-backend.c
View file

@ -163,7 +163,7 @@ static struct XenLegacyDevice *xen_be_get_xendev(const char *type, int dom,
/* init new xendev */
xendev = g_malloc0(ops->size);
object_initialize(&xendev->qdev, ops->size, TYPE_XENBACKEND);
object_initialize(xendev, ops->size, TYPE_XENBACKEND);
OBJECT(xendev)->free = g_free;
qdev_set_id(DEVICE(xendev), g_strdup_printf("xen-%s-%d", type, dev),
&error_fatal);
@ -640,16 +640,14 @@ static void xendev_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
/* xen-backend devices can be plugged/unplugged dynamically */
dc->user_creatable = true;
dc->bus_type = TYPE_XENSYSBUS;
}
static const TypeInfo xendev_type_info = {
.name = TYPE_XENBACKEND,
.parent = TYPE_DEVICE,
.parent = TYPE_DYNAMIC_SYS_BUS_DEVICE,
.class_init = xendev_class_init,
.instance_size = sizeof(struct XenLegacyDevice),
.instance_size = sizeof(XenLegacyDevice),
};
static void xen_sysbus_class_init(ObjectClass *klass, void *data)
@ -672,7 +670,6 @@ static const TypeInfo xensysbus_info = {
static const TypeInfo xensysdev_info = {
.name = TYPE_XENSYSDEV,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SysBusDevice),
};
static void xenbe_register_types(void)

2
hw/xen/xen_pvdev.c
View file

@ -273,7 +273,7 @@ void xen_pv_del_xendev(struct XenLegacyDevice *xendev)
QTAILQ_REMOVE(&xendevs, xendev, next);
qdev_unplug(&xendev->qdev, NULL);
qdev_unplug(DEVICE(xendev), NULL);
}
void xen_pv_insert_xendev(struct XenLegacyDevice *xendev)

2
include/hw/boards.h
View file

@ -283,9 +283,9 @@ struct MachineClass {
no_parallel:1,
no_floppy:1,
no_cdrom:1,
no_sdcard:1,
pci_allow_0_address:1,
legacy_fw_cfg_order:1;
bool auto_create_sdcard;
bool is_default;
const char *default_machine_opts;
const char *default_boot_order;

7
include/hw/qdev-properties-system.h
View file

@ -30,6 +30,7 @@ extern const PropertyInfo qdev_prop_pcie_link_speed;
extern const PropertyInfo qdev_prop_pcie_link_width;
extern const PropertyInfo qdev_prop_cpus390entitlement;
extern const PropertyInfo qdev_prop_iothread_vq_mapping_list;
extern const PropertyInfo qdev_prop_endian_mode;
#define DEFINE_PROP_PCI_DEVFN(_n, _s, _f, _d) \
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pci_devfn, int32_t)
@ -97,4 +98,10 @@ extern const PropertyInfo qdev_prop_iothread_vq_mapping_list;
DEFINE_PROP(_name, _state, _field, qdev_prop_iothread_vq_mapping_list, \
IOThreadVirtQueueMappingList *)
#define DEFINE_PROP_ENDIAN(_name, _state, _field, _default) \
DEFINE_PROP_UNSIGNED(_name, _state, _field, _default, \
qdev_prop_endian_mode, EndianMode)
#define DEFINE_PROP_ENDIAN_NODEFAULT(_name, _state, _field) \
DEFINE_PROP_ENDIAN(_name, _state, _field, ENDIAN_MODE_UNSPECIFIED)
#endif

2
include/hw/sysbus.h
View file

@ -19,6 +19,8 @@ DECLARE_INSTANCE_CHECKER(BusState, SYSTEM_BUS,
OBJECT_DECLARE_TYPE(SysBusDevice, SysBusDeviceClass,
SYS_BUS_DEVICE)
#define TYPE_DYNAMIC_SYS_BUS_DEVICE "dynamic-sysbus-device"
/**
* SysBusDeviceClass:
*

5
include/hw/xen/xen_pvdev.h
View file

@ -1,7 +1,7 @@
#ifndef QEMU_HW_XEN_PVDEV_H
#define QEMU_HW_XEN_PVDEV_H
#include "hw/qdev-core.h"
#include "hw/sysbus.h"
#include "hw/xen/xen_backend_ops.h"
/* ------------------------------------------------------------- */
@ -32,7 +32,8 @@ struct XenDevOps {
};
struct XenLegacyDevice {
DeviceState qdev;
SysBusDevice parent_obj;
const char *type;
int dom;
int dev;

14
qapi/common.json
View file

@ -212,3 +212,17 @@
##
{ 'struct': 'HumanReadableText',
'data': { 'human-readable-text': 'str' } }
##
# @EndianMode:
#
# @unspecified: Endianness not specified
#
# @little: Little endianness
#
# @big: Big endianness
#
# Since: 10.0
##
{ 'enum': 'EndianMode',
'data': [ 'unspecified', 'little', 'big' ] }

24
system/vl.c
View file

@ -53,6 +53,7 @@
#include "hw/usb.h"
#include "hw/isa/isa.h"
#include "hw/scsi/scsi.h"
#include "hw/sd/sd.h"
#include "hw/display/vga.h"
#include "hw/firmware/smbios.h"
#include "hw/acpi/acpi.h"
@ -194,7 +195,7 @@ static int default_parallel = 1;
static int default_monitor = 1;
static int default_floppy = 1;
static int default_cdrom = 1;
static int default_sdcard = 1;
static bool auto_create_sdcard = true;
static int default_vga = 1;
static int default_net = 1;
@ -718,7 +719,7 @@ static void configure_blockdev(BlockdevOptionsQueue *bdo_queue,
default_drive(default_cdrom, snapshot, machine_class->block_default_type, 2,
CDROM_OPTS);
default_drive(default_floppy, snapshot, IF_FLOPPY, 0, FD_OPTS);
default_drive(default_sdcard, snapshot, IF_SD, 0, SD_OPTS);
default_drive(auto_create_sdcard, snapshot, IF_SD, 0, SD_OPTS);
}
@ -1346,8 +1347,8 @@ static void qemu_disable_default_devices(void)
if (!has_defaults || machine_class->no_cdrom) {
default_cdrom = 0;
}
if (!has_defaults || machine_class->no_sdcard) {
default_sdcard = 0;
if (!has_defaults || !machine_class->auto_create_sdcard) {
auto_create_sdcard = false;
}
if (!has_defaults) {
default_audio = 0;
@ -2661,12 +2662,27 @@ static void qemu_init_displays(void)
static void qemu_init_board(void)
{
MachineClass *machine_class = MACHINE_GET_CLASS(current_machine);
/* process plugin before CPUs are created, but once -smp has been parsed */
qemu_plugin_load_list(&plugin_list, &error_fatal);
/* From here on we enter MACHINE_PHASE_INITIALIZED. */
machine_run_board_init(current_machine, mem_path, &error_fatal);
if (machine_class->auto_create_sdcard) {
bool ambigous;
/* Ensure there is a SD bus available to create SD card on */
Object *obj = object_resolve_path_type("", TYPE_SD_BUS, &ambigous);
if (!obj && !ambigous) {
fprintf(stderr, "Can not create sd-card on '%s' machine"
" because it lacks a sd-bus\n",
machine_class->name);
abort();
}
}
drive_check_orphaned();
realtime_init();

11
tests/functional/test_microblaze_s3adsp1800.py
View file

@ -15,14 +15,14 @@ class MicroblazeMachine(QemuSystemTest):
timeout = 90
ASSET_IMAGE = Asset(
ASSET_IMAGE_BE = Asset(
('https://qemu-advcal.gitlab.io/qac-best-of-multiarch/download/'
'day17.tar.xz'),
'3ba7439dfbea7af4876662c97f8e1f0cdad9231fc166e4861d17042489270057')
def test_microblaze_s3adsp1800(self):
self.set_machine('petalogix-s3adsp1800')
self.archive_extract(self.ASSET_IMAGE)
def do_ballerina_be_test(self, machine):
self.set_machine(machine)
self.archive_extract(self.ASSET_IMAGE_BE)
self.vm.set_console()
self.vm.add_args('-kernel',
self.scratch_file('day17', 'ballerina.bin'))
@ -34,5 +34,8 @@ class MicroblazeMachine(QemuSystemTest):
# message, that's why we don't test for a later string here. This
# needs some investigation by a microblaze wizard one day...
def test_microblaze_s3adsp1800_legacy_be(self):
self.do_ballerina_be_test('petalogix-s3adsp1800')
if __name__ == '__main__':
QemuSystemTest.main()

19
tests/functional/test_microblazeel_s3adsp1800.py
View file

@ -7,8 +7,7 @@
# This work is licensed under the terms of the GNU GPL, version 2 or
# later. See the COPYING file in the top-level directory.
import time
from qemu_test import exec_command, exec_command_and_wait_for_pattern
from qemu_test import exec_command_and_wait_for_pattern
from qemu_test import QemuSystemTest, Asset
from qemu_test import wait_for_console_pattern
@ -17,26 +16,28 @@ class MicroblazeelMachine(QemuSystemTest):
timeout = 90
ASSET_IMAGE = Asset(
ASSET_IMAGE_LE = Asset(
('http://www.qemu-advent-calendar.org/2023/download/day13.tar.gz'),
'b9b3d43c5dd79db88ada495cc6e0d1f591153fe41355e925d791fbf44de50c22')
def test_microblazeel_s3adsp1800(self):
def do_xmaton_le_test(self, machine):
self.require_netdev('user')
self.set_machine('petalogix-s3adsp1800')
self.archive_extract(self.ASSET_IMAGE)
self.set_machine(machine)
self.archive_extract(self.ASSET_IMAGE_LE)
self.vm.set_console()
self.vm.add_args('-kernel', self.scratch_file('day13', 'xmaton.bin'))
tftproot = self.scratch_file('day13')
self.vm.add_args('-nic', f'user,tftp={tftproot}')
self.vm.launch()
wait_for_console_pattern(self, 'QEMU Advent Calendar 2023')
time.sleep(0.1)
exec_command(self, 'root')
time.sleep(0.1)
wait_for_console_pattern(self, 'buildroot login:')
exec_command_and_wait_for_pattern(self, 'root', '#')
exec_command_and_wait_for_pattern(self,
'tftp -g -r xmaton.png 10.0.2.2 ; md5sum xmaton.png',
'821cd3cab8efd16ad6ee5acc3642a8ea')
def test_microblaze_s3adsp1800_legacy_le(self):
self.do_xmaton_le_test('petalogix-s3adsp1800')
if __name__ == '__main__':
QemuSystemTest.main()

60
tests/qemu-iotests/172.out
View file

@ -68,9 +68,6 @@ floppy0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -125,9 +122,6 @@ ide1-cd0: [not inserted]
floppy0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -183,9 +177,6 @@ floppy1 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -265,9 +256,6 @@ floppy0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -322,9 +310,6 @@ ide1-cd0: [not inserted]
floppy0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -380,9 +365,6 @@ floppy1 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -422,9 +404,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -461,9 +440,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -519,9 +495,6 @@ none1 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -586,9 +559,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -644,9 +614,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -702,9 +669,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -760,9 +724,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -827,9 +788,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -885,9 +843,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2.2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -930,9 +885,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -1106,9 +1058,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -1145,9 +1094,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -1187,9 +1133,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit
@ -1226,9 +1169,6 @@ none0 (NODE_NAME): TEST_DIR/t.qcow2 (qcow2)
ide1-cd0: [not inserted]
Attached to: /machine/unattached/device[N]
Removable device: not locked, tray closed
sd0: [not inserted]
Removable device: not locked, tray closed
(qemu) quit