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target-arm queue:

Browse source 
* raspi: Implement Broadcom Serial Controller (BSC) for BCM2835 boards
  * hw/char/pl011: Add support for loopback
  * STM32L4x5: Implement RCC clock control device
  * target/arm: Do memory type alignment checks
  * atomic.h: Reword confusing comment for qatomic_cmpxchg
  * qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports
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Merge tag 'pull-target-arm-20240305' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * raspi: Implement Broadcom Serial Controller (BSC) for BCM2835 boards
 * hw/char/pl011: Add support for loopback
 * STM32L4x5: Implement RCC clock control device
 * target/arm: Do memory type alignment checks
 * atomic.h: Reword confusing comment for qatomic_cmpxchg
 * qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports

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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 05 Mar 2024 13:52:08 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240305' of https://git.linaro.org/people/pmaydell/qemu-arm:
  qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports
  atomic.h: Reword confusing comment for qatomic_cmpxchg
  target/arm: Do memory type alignment check when translation enabled
  target/arm: Do memory type alignment check when translation disabled
  accel/tcg: Add TLB_CHECK_ALIGNED
  accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull
  exec/memattrs: Remove target_tlb_bit*
  target/arm: Support 32-byte alignment in pow2_align
  tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCC
  hw/arm/stm32l4x5_soc.c: Use the RCC Sysclk
  hw/misc/stm32l4x5_rcc: Add write protections to CR register
  hw/misc/stm32l4x5_rcc: Handle Register Updates
  hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers
  hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object
  hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer object
  hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeleton
  hw/char/pl011: Add support for loopback
  tests/qtest: Add testcase for BCM2835 BSC
  hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2
  hw/i2c: Implement Broadcom Serial Controller (BSC)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-03-05 13:54:54 +00:00
commit db596ae190
33 changed files with 3718 additions and 84 deletions
Download patch file Download diff file Expand all files Collapse all files

115
tests/qtest/bcm2835-i2c-test.c Normal file
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@ -0,0 +1,115 @@
/*
* QTest testcase for Broadcom Serial Controller (BSC)
*
* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
*
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "libqtest-single.h"
#include "hw/i2c/bcm2835_i2c.h"
#include "hw/sensor/tmp105_regs.h"
static const uint32_t bsc_base_addrs[] = {
0x3f205000, /* I2C0 */
0x3f804000, /* I2C1 */
0x3f805000, /* I2C2 */
};
static void bcm2835_i2c_init_transfer(uint32_t base_addr, bool read)
{
/* read flag is bit 0 so we can write it directly */
int interrupt = read ? BCM2835_I2C_C_INTR : BCM2835_I2C_C_INTT;
writel(base_addr + BCM2835_I2C_C,
BCM2835_I2C_C_I2CEN | BCM2835_I2C_C_INTD |
BCM2835_I2C_C_ST | BCM2835_I2C_C_CLEAR | interrupt | read);
}
static void test_i2c_read_write(gconstpointer data)
{
uint32_t i2cdata;
intptr_t index = (intptr_t) data;
uint32_t base_addr = bsc_base_addrs[index];
/* Write to TMP105 register */
writel(base_addr + BCM2835_I2C_A, 0x50);
writel(base_addr + BCM2835_I2C_DLEN, 3);
bcm2835_i2c_init_transfer(base_addr, 0);
writel(base_addr + BCM2835_I2C_FIFO, TMP105_REG_T_HIGH);
writel(base_addr + BCM2835_I2C_FIFO, 0xde);
writel(base_addr + BCM2835_I2C_FIFO, 0xad);
/* Clear flags */
writel(base_addr + BCM2835_I2C_S, BCM2835_I2C_S_DONE | BCM2835_I2C_S_ERR |
BCM2835_I2C_S_CLKT);
/* Read from TMP105 register */
writel(base_addr + BCM2835_I2C_A, 0x50);
writel(base_addr + BCM2835_I2C_DLEN, 1);
bcm2835_i2c_init_transfer(base_addr, 0);
writel(base_addr + BCM2835_I2C_FIFO, TMP105_REG_T_HIGH);
writel(base_addr + BCM2835_I2C_DLEN, 2);
bcm2835_i2c_init_transfer(base_addr, 1);
i2cdata = readl(base_addr + BCM2835_I2C_FIFO);
g_assert_cmpint(i2cdata, ==, 0xde);
i2cdata = readl(base_addr + BCM2835_I2C_FIFO);
g_assert_cmpint(i2cdata, ==, 0xad);
/* Clear flags */
writel(base_addr + BCM2835_I2C_S, BCM2835_I2C_S_DONE | BCM2835_I2C_S_ERR |
BCM2835_I2C_S_CLKT);
}
int main(int argc, char **argv)
{
int ret;
int i;
g_test_init(&argc, &argv, NULL);
for (i = 0; i < 3; i++) {
g_autofree char *test_name =
g_strdup_printf("/bcm2835/bcm2835-i2c%d/read_write", i);
qtest_add_data_func(test_name, (void *)(intptr_t) i,
test_i2c_read_write);
}
/* Run I2C tests with TMP105 slaves on all three buses */
qtest_start("-M raspi3b "
"-device tmp105,address=0x50,bus=i2c-bus.0 "
"-device tmp105,address=0x50,bus=i2c-bus.1 "
"-device tmp105,address=0x50,bus=i2c-bus.2");
ret = g_test_run();
qtest_end();
return ret;
}

5
tests/qtest/meson.build
View file

@ -203,7 +203,8 @@ qtests_aspeed = \
qtests_stm32l4x5 = \
['stm32l4x5_exti-test',
'stm32l4x5_syscfg-test']
'stm32l4x5_syscfg-test',
'stm32l4x5_rcc-test']
qtests_arm = \
(config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
@ -230,7 +231,7 @@ qtests_aarch64 = \
['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_VERSAL') ? ['xlnx-canfd-test', 'xlnx-versal-trng-test'] : []) + \
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test', 'bcm2835-i2c-test'] : []) + \
(config_all_accel.has_key('CONFIG_TCG') and \
config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \
['arm-cpu-features',

189
tests/qtest/stm32l4x5_rcc-test.c Normal file
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@ -0,0 +1,189 @@
/*
* QTest testcase for STM32L4x5_RCC
*
* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "hw/registerfields.h"
#include "libqtest-single.h"
#include "hw/misc/stm32l4x5_rcc_internals.h"
#define RCC_BASE_ADDR 0x40021000
#define NVIC_ISER 0xE000E100
#define NVIC_ISPR 0xE000E200
#define NVIC_ICPR 0xE000E280
#define RCC_IRQ 5
static void enable_nvic_irq(unsigned int n)
{
writel(NVIC_ISER, 1 << n);
}
static void unpend_nvic_irq(unsigned int n)
{
writel(NVIC_ICPR, 1 << n);
}
static bool check_nvic_pending(unsigned int n)
{
return readl(NVIC_ISPR) & (1 << n);
}
static void rcc_writel(unsigned int offset, uint32_t value)
{
writel(RCC_BASE_ADDR + offset, value);
}
static uint32_t rcc_readl(unsigned int offset)
{
return readl(RCC_BASE_ADDR + offset);
}
static void test_init_msi(void)
{
/* MSIRANGE can be set only when MSI is OFF or READY */
rcc_writel(A_CR, R_CR_MSION_MASK);
/* Wait until MSI is stable */
g_assert_true((rcc_readl(A_CR) & R_CR_MSIRDY_MASK) == R_CR_MSIRDY_MASK);
/* TODO find a way to test MSI value */
}
static void test_set_msi_as_sysclk(void)
{
/* Clocking from MSI, in case MSI was not the default source */
rcc_writel(A_CFGR, 0);
/* Wait until MSI is selected and stable */
g_assert_true((rcc_readl(A_CFGR) & R_CFGR_SWS_MASK) == 0);
}
static void test_init_pll(void)
{
uint32_t value;
/*
* Update PLL and set MSI as the source clock.
* PLLM = 1 --> 000
* PLLN = 40 --> 40
* PPLLR = 2 --> 00
* PLLDIV = unused, PLLP = unused (SAI3), PLLQ = unused (48M1)
* SRC = MSI --> 01
*/
rcc_writel(A_PLLCFGR, R_PLLCFGR_PLLREN_MASK |
(40 << R_PLLCFGR_PLLN_SHIFT) |
(0b01 << R_PLLCFGR_PLLSRC_SHIFT));
/* PLL activation */
value = rcc_readl(A_CR);
rcc_writel(A_CR, value | R_CR_PLLON_MASK);
/* Waiting for PLL lock. */
g_assert_true((rcc_readl(A_CR) & R_CR_PLLRDY_MASK) == R_CR_PLLRDY_MASK);
/* Switches on the PLL clock source */
value = rcc_readl(A_CFGR);
rcc_writel(A_CFGR, (value & ~R_CFGR_SW_MASK) |
(0b11 << R_CFGR_SW_SHIFT));
/* Wait until SYSCLK is stable. */
g_assert_true((rcc_readl(A_CFGR) & R_CFGR_SWS_MASK) ==
(0b11 << R_CFGR_SWS_SHIFT));
}
static void test_activate_lse(void)
{
/* LSE activation, no LSE Bypass */
rcc_writel(A_BDCR, R_BDCR_LSEDRV_MASK | R_BDCR_LSEON_MASK);
g_assert_true((rcc_readl(A_BDCR) & R_BDCR_LSERDY_MASK) == R_BDCR_LSERDY_MASK);
}
static void test_irq(void)
{
enable_nvic_irq(RCC_IRQ);
rcc_writel(A_CIER, R_CIER_LSIRDYIE_MASK);
rcc_writel(A_CSR, R_CSR_LSION_MASK);
g_assert_true(check_nvic_pending(RCC_IRQ));
rcc_writel(A_CICR, R_CICR_LSIRDYC_MASK);
unpend_nvic_irq(RCC_IRQ);
rcc_writel(A_CIER, R_CIER_LSERDYIE_MASK);
rcc_writel(A_BDCR, R_BDCR_LSEON_MASK);
g_assert_true(check_nvic_pending(RCC_IRQ));
rcc_writel(A_CICR, R_CICR_LSERDYC_MASK);
unpend_nvic_irq(RCC_IRQ);
/*
* MSI has been enabled by previous tests,
* shouln't generate an interruption.
*/
rcc_writel(A_CIER, R_CIER_MSIRDYIE_MASK);
rcc_writel(A_CR, R_CR_MSION_MASK);
g_assert_false(check_nvic_pending(RCC_IRQ));
rcc_writel(A_CIER, R_CIER_HSIRDYIE_MASK);
rcc_writel(A_CR, R_CR_HSION_MASK);
g_assert_true(check_nvic_pending(RCC_IRQ));
rcc_writel(A_CICR, R_CICR_HSIRDYC_MASK);
unpend_nvic_irq(RCC_IRQ);
rcc_writel(A_CIER, R_CIER_HSERDYIE_MASK);
rcc_writel(A_CR, R_CR_HSEON_MASK);
g_assert_true(check_nvic_pending(RCC_IRQ));
rcc_writel(A_CICR, R_CICR_HSERDYC_MASK);
unpend_nvic_irq(RCC_IRQ);
/*
* PLL has been enabled by previous tests,
* shouln't generate an interruption.
*/
rcc_writel(A_CIER, R_CIER_PLLRDYIE_MASK);
rcc_writel(A_CR, R_CR_PLLON_MASK);
g_assert_false(check_nvic_pending(RCC_IRQ));
rcc_writel(A_CIER, R_CIER_PLLSAI1RDYIE_MASK);
rcc_writel(A_CR, R_CR_PLLSAI1ON_MASK);
g_assert_true(check_nvic_pending(RCC_IRQ));
rcc_writel(A_CICR, R_CICR_PLLSAI1RDYC_MASK);
unpend_nvic_irq(RCC_IRQ);
rcc_writel(A_CIER, R_CIER_PLLSAI2RDYIE_MASK);
rcc_writel(A_CR, R_CR_PLLSAI2ON_MASK);
g_assert_true(check_nvic_pending(RCC_IRQ));
rcc_writel(A_CICR, R_CICR_PLLSAI2RDYC_MASK);
unpend_nvic_irq(RCC_IRQ);
}
int main(int argc, char **argv)
{
int ret;
g_test_init(&argc, &argv, NULL);
g_test_set_nonfatal_assertions();
/*
* These test separately that we can enable the plls, change the sysclk,
* and enable different devices.
* They are dependent on one another.
* We assume that all operations that would take some time to have an effect
* (e.g. changing the PLL frequency) are done instantaneously.
*/
qtest_add_func("stm32l4x5/rcc/init_msi", test_init_msi);
qtest_add_func("stm32l4x5/rcc/set_msi_as_sysclk",
test_set_msi_as_sysclk);
qtest_add_func("stm32l4x5/rcc/activate_lse", test_activate_lse);
qtest_add_func("stm32l4x5/rcc/init_pll", test_init_pll);
qtest_add_func("stm32l4x5/rcc/irq", test_irq);
qtest_start("-machine b-l475e-iot01a");
ret = g_test_run();
qtest_end();
return ret;
}