mirror of
https://github.com/Motorhead1991/qemu.git
synced 2026-03-04 09:04:39 -07:00
target-arm queue:
* raspi: Implement Broadcom Serial Controller (BSC) for BCM2835 boards * hw/char/pl011: Add support for loopback * STM32L4x5: Implement RCC clock control device * target/arm: Do memory type alignment checks * atomic.h: Reword confusing comment for qatomic_cmpxchg * qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXnI4gZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3p5ED/wOtAHA3PK+WbQhVhnji3+k gdhvVcldf+HLaI2v4tfaW152xjY80/j3PQFNkzptoXENA9U51F47oNYOIfULLZZX FTKmw/mjTBc2LqJ8gLpS8Wkr/PFtDq9JJzDwZd0MwguXpzIJp31JJpESvXlAqjjv FhuAcqNNuGwI2SXCBmp2lPoEMn8ExLDoG9rmzjxVZeZCyzUjVnJYM61ykhC4ByvK j5+/a7pUcpgHSX5cbq7kFloPOx3JXI5lS6xUKhGXXk75qHRwiQIsxMcPq8PD1+ok yrmp7cySwK8I7AlIPdDjpJmhU0OiBu+PkYiXmHlF2nvaUy6M0nVX2lSTzqj6VpVV 7yYhvWXHrtIA9AUspqTRsX7tP7iMJkco7qWfKSzYl+3pTbxS4+rEoee4jNR3hqsU lbWC47sNVtTN507qIL1dcsu+BaeSsYVftfxtFql3odTqRB+ticsjDfKg69dRSFyk SS0t8Zy3TdomcEoQkAv/ZSpkQnQUGavbRumCG58lJdiTwTuJUmGi1ufKBrD/GeKj IlDEl9yvKiR8uvdjj6EQqr5kOj09mmN5nvokNsq5a4aNXBYoesszWK2xodzXE2x5 M9DHJ3S8xnN++p1idS2bikwEklG1XVQ/q52bDXQkUmQSNerVS1PCvg9hzYqA+x53 ihJtMcsmGVfxY8aQHyHweA== =isAe -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20240305' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * raspi: Implement Broadcom Serial Controller (BSC) for BCM2835 boards * hw/char/pl011: Add support for loopback * STM32L4x5: Implement RCC clock control device * target/arm: Do memory type alignment checks * atomic.h: Reword confusing comment for qatomic_cmpxchg * qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXnI4gZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3p5ED/wOtAHA3PK+WbQhVhnji3+k # gdhvVcldf+HLaI2v4tfaW152xjY80/j3PQFNkzptoXENA9U51F47oNYOIfULLZZX # FTKmw/mjTBc2LqJ8gLpS8Wkr/PFtDq9JJzDwZd0MwguXpzIJp31JJpESvXlAqjjv # FhuAcqNNuGwI2SXCBmp2lPoEMn8ExLDoG9rmzjxVZeZCyzUjVnJYM61ykhC4ByvK # j5+/a7pUcpgHSX5cbq7kFloPOx3JXI5lS6xUKhGXXk75qHRwiQIsxMcPq8PD1+ok # yrmp7cySwK8I7AlIPdDjpJmhU0OiBu+PkYiXmHlF2nvaUy6M0nVX2lSTzqj6VpVV # 7yYhvWXHrtIA9AUspqTRsX7tP7iMJkco7qWfKSzYl+3pTbxS4+rEoee4jNR3hqsU # lbWC47sNVtTN507qIL1dcsu+BaeSsYVftfxtFql3odTqRB+ticsjDfKg69dRSFyk # SS0t8Zy3TdomcEoQkAv/ZSpkQnQUGavbRumCG58lJdiTwTuJUmGi1ufKBrD/GeKj # IlDEl9yvKiR8uvdjj6EQqr5kOj09mmN5nvokNsq5a4aNXBYoesszWK2xodzXE2x5 # M9DHJ3S8xnN++p1idS2bikwEklG1XVQ/q52bDXQkUmQSNerVS1PCvg9hzYqA+x53 # ihJtMcsmGVfxY8aQHyHweA== # =isAe # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Mar 2024 13:52:08 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240305' of https://git.linaro.org/people/pmaydell/qemu-arm: qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports atomic.h: Reword confusing comment for qatomic_cmpxchg target/arm: Do memory type alignment check when translation enabled target/arm: Do memory type alignment check when translation disabled accel/tcg: Add TLB_CHECK_ALIGNED accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull exec/memattrs: Remove target_tlb_bit* target/arm: Support 32-byte alignment in pow2_align tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCC hw/arm/stm32l4x5_soc.c: Use the RCC Sysclk hw/misc/stm32l4x5_rcc: Add write protections to CR register hw/misc/stm32l4x5_rcc: Handle Register Updates hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer object hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeleton hw/char/pl011: Add support for loopback tests/qtest: Add testcase for BCM2835 BSC hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2 hw/i2c: Implement Broadcom Serial Controller (BSC) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
db596ae190
33 changed files with 3718 additions and 84 deletions
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@ -357,8 +357,10 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
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#define TLB_BSWAP (1 << 0)
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/* Set if TLB entry contains a watchpoint. */
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#define TLB_WATCHPOINT (1 << 1)
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/* Set if TLB entry requires aligned accesses. */
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#define TLB_CHECK_ALIGNED (1 << 2)
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#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT)
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#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED)
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/* The two sets of flags must not overlap. */
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QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
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@ -52,18 +52,6 @@ typedef struct MemTxAttrs {
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unsigned int memory:1;
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/* Requester ID (for MSI for example) */
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unsigned int requester_id:16;
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/* Invert endianness for this page */
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unsigned int byte_swap:1;
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/*
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* The following are target-specific page-table bits. These are not
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* related to actual memory transactions at all. However, this structure
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* is part of the tlb_fill interface, cached in the cputlb structure,
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* and has unused bits. These fields will be read by target-specific
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* helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN.
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*/
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unsigned int target_tlb_bit0 : 1;
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unsigned int target_tlb_bit1 : 1;
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unsigned int target_tlb_bit2 : 1;
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} MemTxAttrs;
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/* Bus masters which don't specify any attributes will get this,
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@ -32,6 +32,7 @@
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#include "hw/timer/bcm2835_systmr.h"
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#include "hw/usb/hcd-dwc2.h"
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#include "hw/ssi/bcm2835_spi.h"
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#include "hw/i2c/bcm2835_i2c.h"
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#include "hw/misc/unimp.h"
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#include "qom/object.h"
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@ -68,7 +69,8 @@ struct BCMSocPeripheralBaseState {
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BCM2835SDHostState sdhost;
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UnimplementedDeviceState i2s;
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BCM2835SPIState spi[1];
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UnimplementedDeviceState i2c[3];
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BCM2835I2CState i2c[3];
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OrIRQState orgated_i2c_irq;
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UnimplementedDeviceState otp;
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UnimplementedDeviceState dbus;
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UnimplementedDeviceState ave0;
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@ -29,6 +29,7 @@
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#include "hw/or-irq.h"
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#include "hw/misc/stm32l4x5_syscfg.h"
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#include "hw/misc/stm32l4x5_exti.h"
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#include "hw/misc/stm32l4x5_rcc.h"
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#include "qom/object.h"
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#define TYPE_STM32L4X5_SOC "stm32l4x5-soc"
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@ -47,14 +48,12 @@ struct Stm32l4x5SocState {
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Stm32l4x5ExtiState exti;
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OrIRQState exti_or_gates[NUM_EXTI_OR_GATES];
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Stm32l4x5SyscfgState syscfg;
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Stm32l4x5RccState rcc;
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MemoryRegion sram1;
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MemoryRegion sram2;
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MemoryRegion flash;
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MemoryRegion flash_alias;
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Clock *sysclk;
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Clock *refclk;
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};
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struct Stm32l4x5SocClass {
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@ -230,6 +230,9 @@ typedef struct CPUTLBEntryFull {
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/* @lg_page_size contains the log2 of the page size. */
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uint8_t lg_page_size;
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/* Additional tlb flags requested by tlb_fill. */
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uint8_t tlb_fill_flags;
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/*
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* Additional tlb flags for use by the slow path. If non-zero,
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* the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW.
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80
include/hw/i2c/bcm2835_i2c.h
Normal file
80
include/hw/i2c/bcm2835_i2c.h
Normal file
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@ -0,0 +1,80 @@
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/*
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* Broadcom Serial Controller (BSC)
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*
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* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h"
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#include "hw/i2c/i2c.h"
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#include "qom/object.h"
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#define TYPE_BCM2835_I2C "bcm2835-i2c"
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OBJECT_DECLARE_SIMPLE_TYPE(BCM2835I2CState, BCM2835_I2C)
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#define BCM2835_I2C_C 0x0 /* Control */
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#define BCM2835_I2C_S 0x4 /* Status */
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#define BCM2835_I2C_DLEN 0x8 /* Data Length */
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#define BCM2835_I2C_A 0xc /* Slave Address */
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#define BCM2835_I2C_FIFO 0x10 /* FIFO */
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#define BCM2835_I2C_DIV 0x14 /* Clock Divider */
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#define BCM2835_I2C_DEL 0x18 /* Data Delay */
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#define BCM2835_I2C_CLKT 0x20 /* Clock Stretch Timeout */
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#define BCM2835_I2C_C_I2CEN BIT(15) /* I2C enable */
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#define BCM2835_I2C_C_INTR BIT(10) /* Interrupt on RXR */
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#define BCM2835_I2C_C_INTT BIT(9) /* Interrupt on TXW */
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#define BCM2835_I2C_C_INTD BIT(8) /* Interrupt on DONE */
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#define BCM2835_I2C_C_ST BIT(7) /* Start transfer */
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#define BCM2835_I2C_C_CLEAR (BIT(5) | BIT(4)) /* Clear FIFO */
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#define BCM2835_I2C_C_READ BIT(0) /* I2C read mode */
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#define BCM2835_I2C_S_CLKT BIT(9) /* Clock stretch timeout */
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#define BCM2835_I2C_S_ERR BIT(8) /* Slave error */
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#define BCM2835_I2C_S_RXF BIT(7) /* RX FIFO full */
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#define BCM2835_I2C_S_TXE BIT(6) /* TX FIFO empty */
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#define BCM2835_I2C_S_RXD BIT(5) /* RX bytes available */
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#define BCM2835_I2C_S_TXD BIT(4) /* TX space available */
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#define BCM2835_I2C_S_RXR BIT(3) /* RX FIFO needs reading */
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#define BCM2835_I2C_S_TXW BIT(2) /* TX FIFO needs writing */
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#define BCM2835_I2C_S_DONE BIT(1) /* I2C Transfer complete */
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#define BCM2835_I2C_S_TA BIT(0) /* I2C Transfer active */
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struct BCM2835I2CState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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I2CBus *bus;
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qemu_irq irq;
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uint32_t c;
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uint32_t s;
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uint32_t dlen;
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uint32_t a;
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uint32_t div;
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uint32_t del;
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uint32_t clkt;
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uint32_t last_dlen;
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};
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239
include/hw/misc/stm32l4x5_rcc.h
Normal file
239
include/hw/misc/stm32l4x5_rcc.h
Normal file
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@ -0,0 +1,239 @@
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/*
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* STM32L4X5 RCC (Reset and clock control)
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*
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* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* The reference used is the STMicroElectronics RM0351 Reference manual
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* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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*
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* Inspired by the BCM2835 CPRMAN clock manager by Luc Michel.
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*/
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#ifndef HW_STM32L4X5_RCC_H
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#define HW_STM32L4X5_RCC_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_STM32L4X5_RCC "stm32l4x5-rcc"
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OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5RccState, STM32L4X5_RCC)
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/* In the Stm32l4x5 clock tree, mux have at most 7 sources */
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#define RCC_NUM_CLOCK_MUX_SRC 7
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typedef enum PllCommonChannels {
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RCC_PLL_COMMON_CHANNEL_P = 0,
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RCC_PLL_COMMON_CHANNEL_Q = 1,
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RCC_PLL_COMMON_CHANNEL_R = 2,
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RCC_NUM_CHANNEL_PLL_OUT = 3
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} PllCommonChannels;
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/* NB: Prescaler are assimilated to mux with one source and one output */
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typedef enum RccClockMux {
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/* Internal muxes that arent't exposed publicly to other peripherals */
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RCC_CLOCK_MUX_SYSCLK,
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RCC_CLOCK_MUX_PLL_INPUT,
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RCC_CLOCK_MUX_HCLK,
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RCC_CLOCK_MUX_PCLK1,
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RCC_CLOCK_MUX_PCLK2,
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RCC_CLOCK_MUX_HSE_OVER_32,
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RCC_CLOCK_MUX_LCD_AND_RTC_COMMON,
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/* Muxes with a publicly available output */
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RCC_CLOCK_MUX_CORTEX_REFCLK,
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RCC_CLOCK_MUX_USART1,
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RCC_CLOCK_MUX_USART2,
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RCC_CLOCK_MUX_USART3,
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RCC_CLOCK_MUX_UART4,
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RCC_CLOCK_MUX_UART5,
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RCC_CLOCK_MUX_LPUART1,
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RCC_CLOCK_MUX_I2C1,
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RCC_CLOCK_MUX_I2C2,
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RCC_CLOCK_MUX_I2C3,
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RCC_CLOCK_MUX_LPTIM1,
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RCC_CLOCK_MUX_LPTIM2,
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RCC_CLOCK_MUX_SWPMI1,
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RCC_CLOCK_MUX_MCO,
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RCC_CLOCK_MUX_LSCO,
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RCC_CLOCK_MUX_DFSDM1,
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RCC_CLOCK_MUX_ADC,
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RCC_CLOCK_MUX_CLK48,
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RCC_CLOCK_MUX_SAI1,
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RCC_CLOCK_MUX_SAI2,
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/*
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* Mux that have only one input and one output assigned to as peripheral.
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* They could be direct lines but it is simpler
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* to use the same logic for all outputs.
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*/
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/* - AHB1 */
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RCC_CLOCK_MUX_TSC,
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RCC_CLOCK_MUX_CRC,
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RCC_CLOCK_MUX_FLASH,
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RCC_CLOCK_MUX_DMA2,
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RCC_CLOCK_MUX_DMA1,
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/* - AHB2 */
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RCC_CLOCK_MUX_RNG,
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RCC_CLOCK_MUX_AES,
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RCC_CLOCK_MUX_OTGFS,
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RCC_CLOCK_MUX_GPIOA,
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RCC_CLOCK_MUX_GPIOB,
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RCC_CLOCK_MUX_GPIOC,
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RCC_CLOCK_MUX_GPIOD,
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RCC_CLOCK_MUX_GPIOE,
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RCC_CLOCK_MUX_GPIOF,
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RCC_CLOCK_MUX_GPIOG,
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RCC_CLOCK_MUX_GPIOH,
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/* - AHB3 */
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RCC_CLOCK_MUX_QSPI,
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RCC_CLOCK_MUX_FMC,
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/* - APB1 */
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RCC_CLOCK_MUX_OPAMP,
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RCC_CLOCK_MUX_DAC1,
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RCC_CLOCK_MUX_PWR,
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RCC_CLOCK_MUX_CAN1,
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RCC_CLOCK_MUX_SPI3,
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RCC_CLOCK_MUX_SPI2,
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RCC_CLOCK_MUX_WWDG,
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RCC_CLOCK_MUX_LCD,
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RCC_CLOCK_MUX_TIM7,
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RCC_CLOCK_MUX_TIM6,
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RCC_CLOCK_MUX_TIM5,
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RCC_CLOCK_MUX_TIM4,
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RCC_CLOCK_MUX_TIM3,
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RCC_CLOCK_MUX_TIM2,
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/* - APB2 */
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RCC_CLOCK_MUX_TIM17,
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RCC_CLOCK_MUX_TIM16,
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RCC_CLOCK_MUX_TIM15,
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RCC_CLOCK_MUX_TIM8,
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RCC_CLOCK_MUX_SPI1,
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RCC_CLOCK_MUX_TIM1,
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RCC_CLOCK_MUX_SDMMC1,
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RCC_CLOCK_MUX_FW,
|
||||
RCC_CLOCK_MUX_SYSCFG,
|
||||
|
||||
/* - BDCR */
|
||||
RCC_CLOCK_MUX_RTC,
|
||||
|
||||
/* - OTHER */
|
||||
RCC_CLOCK_MUX_CORTEX_FCLK,
|
||||
|
||||
RCC_NUM_CLOCK_MUX
|
||||
} RccClockMux;
|
||||
|
||||
typedef enum RccPll {
|
||||
RCC_PLL_PLL,
|
||||
RCC_PLL_PLLSAI1,
|
||||
RCC_PLL_PLLSAI2,
|
||||
|
||||
RCC_NUM_PLL
|
||||
} RccPll;
|
||||
|
||||
typedef struct RccClockMuxState {
|
||||
DeviceState parent_obj;
|
||||
|
||||
RccClockMux id;
|
||||
Clock *srcs[RCC_NUM_CLOCK_MUX_SRC];
|
||||
Clock *out;
|
||||
bool enabled;
|
||||
uint32_t src;
|
||||
uint32_t multiplier;
|
||||
uint32_t divider;
|
||||
|
||||
/*
|
||||
* Used by clock srcs update callback to retrieve both the clock and the
|
||||
* source number.
|
||||
*/
|
||||
struct RccClockMuxState *backref[RCC_NUM_CLOCK_MUX_SRC];
|
||||
} RccClockMuxState;
|
||||
|
||||
typedef struct RccPllState {
|
||||
DeviceState parent_obj;
|
||||
|
||||
RccPll id;
|
||||
Clock *in;
|
||||
uint32_t vco_multiplier;
|
||||
Clock *channels[RCC_NUM_CHANNEL_PLL_OUT];
|
||||
/* Global pll enabled flag */
|
||||
bool enabled;
|
||||
/* 'enabled' refers to the runtime configuration */
|
||||
bool channel_enabled[RCC_NUM_CHANNEL_PLL_OUT];
|
||||
/*
|
||||
* 'exists' refers to the physical configuration
|
||||
* It should only be set at pll initialization.
|
||||
* e.g. pllsai2 doesn't have a Q output.
|
||||
*/
|
||||
bool channel_exists[RCC_NUM_CHANNEL_PLL_OUT];
|
||||
uint32_t channel_divider[RCC_NUM_CHANNEL_PLL_OUT];
|
||||
} RccPllState;
|
||||
|
||||
struct Stm32l4x5RccState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
MemoryRegion mmio;
|
||||
|
||||
uint32_t cr;
|
||||
uint32_t icscr;
|
||||
uint32_t cfgr;
|
||||
uint32_t pllcfgr;
|
||||
uint32_t pllsai1cfgr;
|
||||
uint32_t pllsai2cfgr;
|
||||
uint32_t cier;
|
||||
uint32_t cifr;
|
||||
uint32_t ahb1rstr;
|
||||
uint32_t ahb2rstr;
|
||||
uint32_t ahb3rstr;
|
||||
uint32_t apb1rstr1;
|
||||
uint32_t apb1rstr2;
|
||||
uint32_t apb2rstr;
|
||||
uint32_t ahb1enr;
|
||||
uint32_t ahb2enr;
|
||||
uint32_t ahb3enr;
|
||||
uint32_t apb1enr1;
|
||||
uint32_t apb1enr2;
|
||||
uint32_t apb2enr;
|
||||
uint32_t ahb1smenr;
|
||||
uint32_t ahb2smenr;
|
||||
uint32_t ahb3smenr;
|
||||
uint32_t apb1smenr1;
|
||||
uint32_t apb1smenr2;
|
||||
uint32_t apb2smenr;
|
||||
uint32_t ccipr;
|
||||
uint32_t bdcr;
|
||||
uint32_t csr;
|
||||
|
||||
/* Clock sources */
|
||||
Clock *gnd;
|
||||
Clock *hsi16_rc;
|
||||
Clock *msi_rc;
|
||||
Clock *hse;
|
||||
Clock *lsi_rc;
|
||||
Clock *lse_crystal;
|
||||
Clock *sai1_extclk;
|
||||
Clock *sai2_extclk;
|
||||
|
||||
/* PLLs */
|
||||
RccPllState plls[RCC_NUM_PLL];
|
||||
|
||||
/* Muxes ~= outputs */
|
||||
RccClockMuxState clock_muxes[RCC_NUM_CLOCK_MUX];
|
||||
|
||||
qemu_irq irq;
|
||||
uint64_t hse_frequency;
|
||||
uint64_t sai1_extclk_frequency;
|
||||
uint64_t sai2_extclk_frequency;
|
||||
};
|
||||
|
||||
#endif /* HW_STM32L4X5_RCC_H */
|
||||
1042
include/hw/misc/stm32l4x5_rcc_internals.h
Normal file
1042
include/hw/misc/stm32l4x5_rcc_internals.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -202,7 +202,7 @@
|
|||
qatomic_xchg__nocheck(ptr, i); \
|
||||
})
|
||||
|
||||
/* Returns the eventual value, failed or not */
|
||||
/* Returns the old value of '*ptr' (whether the cmpxchg failed or not) */
|
||||
#define qatomic_cmpxchg__nocheck(ptr, old, new) ({ \
|
||||
typeof_strip_qual(*ptr) _old = (old); \
|
||||
(void)__atomic_compare_exchange_n(ptr, &_old, new, false, \
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue