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spapr: add an extra OV5 field to the sPAPR IRQ backend
The interrupt modes supported by the hypervisor are advertised to the guest with new bits definitions of the option vector 5 of property "ibm,arch-vec-5-platform-support. The byte 23 bits 0-1 of the OV5 are defined as follow : 0b00 PAPR 2.7 and earlier (Legacy systems) 0b01 XIVE Exploitation mode only 0b10 Either available If the client/guest selects the XIVE interrupt mode, it informs the hypervisor by returning the value 0b01 in byte 23 bits 0-1. A 0b00 value indicates the use of the XICS interrupt mode (Legacy systems). The sPAPR IRQ backend is extended with these definitions and the values are directly used to populate the "ibm,arch-vec-5-platform-support" property. The interrupt mode is advertised under TCG and under KVM. Although a KVM XIVE device is not yet available, the machine can still operate with kernel_irqchip=off. However, we apply a restriction on the CPU which is required to be a POWER9 when a XIVE interrupt controller is in use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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4 changed files with 36 additions and 7 deletions
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@ -216,6 +216,7 @@ static int spapr_irq_post_load_xics(sPAPRMachineState *spapr, int version_id)
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sPAPRIrq spapr_irq_xics = {
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.nr_irqs = SPAPR_IRQ_XICS_NR_IRQS,
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.nr_msis = SPAPR_IRQ_XICS_NR_MSIS,
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.ov5 = SPAPR_OV5_XIVE_LEGACY,
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.init = spapr_irq_init_xics,
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.claim = spapr_irq_claim_xics,
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@ -343,6 +344,7 @@ static void spapr_irq_reset_xive(sPAPRMachineState *spapr, Error **errp)
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sPAPRIrq spapr_irq_xive = {
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.nr_irqs = SPAPR_IRQ_XIVE_NR_IRQS,
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.nr_msis = SPAPR_IRQ_XIVE_NR_MSIS,
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.ov5 = SPAPR_OV5_XIVE_EXPLOIT,
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.init = spapr_irq_init_xive,
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.claim = spapr_irq_claim_xive,
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@ -467,6 +469,7 @@ int spapr_irq_find(sPAPRMachineState *spapr, int num, bool align, Error **errp)
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sPAPRIrq spapr_irq_xics_legacy = {
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.nr_irqs = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
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.nr_msis = SPAPR_IRQ_XICS_LEGACY_NR_IRQS,
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.ov5 = SPAPR_OV5_XIVE_LEGACY,
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.init = spapr_irq_init_xics,
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.claim = spapr_irq_claim_xics,
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