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target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

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Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.

Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-10-19 20:16:58 -07:00 • committed by Alistair Francis
parent e91a7227cb
commit db23e5d981
8 changed files with 45 additions and 34 deletions
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2
semihosting/arm-compat-semi.c
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@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env)
#if defined(TARGET_ARM)
return is_a64(env);
#elif defined(TARGET_RISCV)
return !riscv_cpu_is_32bit(env);
return riscv_cpu_mxl(env) != MXL_RV32;
#else
#error un-handled architecture
#endif