mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-05 00:33:55 -06:00
Move QOM typedefs and add missing includes
Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.
Patch generated using:
$ ./scripts/codeconverter/converter.py -i \
--pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')
which will split "typdef struct { ... } TypedefName"
declarations.
Followed by:
$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
$(git grep -l '' -- '*.[ch]')
which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Eduardo Habkost
parent
1c8eef0227
commit
db1015e92e
796 changed files with 3378 additions and 1823 deletions
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@ -14,6 +14,7 @@
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#include "hw/rtc/allwinner-rtc.h"
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#include "target/arm/cpu.h"
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#include "qom/object.h"
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#define AW_A10_SDRAM_BASE 0x40000000
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@ -21,9 +22,10 @@
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#define AW_A10_NUM_USB 2
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#define TYPE_AW_A10 "allwinner-a10"
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typedef struct AwA10State AwA10State;
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#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
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typedef struct AwA10State {
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struct AwA10State {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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@ -38,6 +40,6 @@ typedef struct AwA10State {
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MemoryRegion sram_a;
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EHCISysBusState ehci[AW_A10_NUM_USB];
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OHCISysBusState ohci[AW_A10_NUM_USB];
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} AwA10State;
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};
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#endif
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@ -106,6 +106,7 @@ enum {
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#define TYPE_AW_H3 "allwinner-h3"
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/** Convert input object to Allwinner H3 state object */
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typedef struct AwH3State AwH3State;
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#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
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/** @} */
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@ -116,7 +117,7 @@ enum {
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* This struct contains the state of all the devices
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* which are currently emulated by the H3 SoC code.
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*/
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typedef struct AwH3State {
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struct AwH3State {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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@ -136,7 +137,7 @@ typedef struct AwH3State {
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MemoryRegion sram_a1;
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MemoryRegion sram_a2;
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MemoryRegion sram_c;
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} AwH3State;
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};
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/**
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* Emulate Boot ROM firmware setup functionality.
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@ -105,8 +105,11 @@
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#include "hw/or-irq.h"
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#include "hw/core/split-irq.h"
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#include "hw/cpu/cluster.h"
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#include "qom/object.h"
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#define TYPE_ARM_SSE "arm-sse"
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typedef struct ARMSSE ARMSSE;
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typedef struct ARMSSEClass ARMSSEClass;
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#define ARM_SSE(obj) OBJECT_CHECK(ARMSSE, (obj), TYPE_ARM_SSE)
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/*
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@ -140,7 +143,7 @@
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#define RAM3_PPU 6
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#define NUM_PPUS 7
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typedef struct ARMSSE {
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struct ARMSSE {
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/*< private >*/
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SysBusDevice parent_obj;
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@ -215,14 +218,14 @@ typedef struct ARMSSE {
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uint32_t init_svtor;
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bool cpu_fpu[SSE_MAX_CPUS];
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bool cpu_dsp[SSE_MAX_CPUS];
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} ARMSSE;
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};
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typedef struct ARMSSEInfo ARMSSEInfo;
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typedef struct ARMSSEClass {
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struct ARMSSEClass {
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SysBusDeviceClass parent_class;
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const ARMSSEInfo *info;
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} ARMSSEClass;
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};
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#define ARM_SSE_CLASS(klass) \
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OBJECT_CLASS_CHECK(ARMSSEClass, (klass), TYPE_ARM_SSE)
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@ -13,11 +13,13 @@
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#include "hw/sysbus.h"
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#include "hw/intc/armv7m_nvic.h"
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#include "target/arm/idau.h"
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#include "qom/object.h"
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#define TYPE_BITBAND "ARM,bitband-memory"
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typedef struct BitBandState BitBandState;
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#define BITBAND(obj) OBJECT_CHECK(BitBandState, (obj), TYPE_BITBAND)
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typedef struct {
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struct BitBandState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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@ -26,9 +28,10 @@ typedef struct {
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MemoryRegion iomem;
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uint32_t base;
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MemoryRegion *source_memory;
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} BitBandState;
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};
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#define TYPE_ARMV7M "armv7m"
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typedef struct ARMv7MState ARMv7MState;
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#define ARMV7M(obj) OBJECT_CHECK(ARMv7MState, (obj), TYPE_ARMV7M)
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#define ARMV7M_NUM_BITBANDS 2
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@ -49,7 +52,7 @@ typedef struct {
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* + Property "dsp": enable DSP (forwarded to CPU object)
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* + Property "enable-bitband": expose bitbanded IO
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*/
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typedef struct ARMv7MState {
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struct ARMv7MState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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@ -72,6 +75,6 @@ typedef struct ARMv7MState {
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bool start_powered_off;
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bool vfp;
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bool dsp;
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} ARMv7MState;
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};
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#endif
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@ -10,10 +10,12 @@
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#define ARM_ASPEED_H
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#include "hw/boards.h"
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#include "qom/object.h"
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typedef struct AspeedMachineState AspeedMachineState;
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#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
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typedef struct AspeedMachineClass AspeedMachineClass;
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#define ASPEED_MACHINE(obj) \
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OBJECT_CHECK(AspeedMachineState, (obj), TYPE_ASPEED_MACHINE)
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@ -27,7 +29,7 @@ typedef struct AspeedMachineState AspeedMachineState;
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#define ASPEED_MACHINE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedMachineClass, (obj), TYPE_ASPEED_MACHINE)
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typedef struct AspeedMachineClass {
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struct AspeedMachineClass {
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MachineClass parent_obj;
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const char *name;
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@ -40,7 +42,7 @@ typedef struct AspeedMachineClass {
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uint32_t num_cs;
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uint32_t macs_mask;
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void (*i2c_init)(AspeedMachineState *bmc);
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} AspeedMachineClass;
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};
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#endif
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@ -27,6 +27,7 @@
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#include "hw/gpio/aspeed_gpio.h"
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#include "hw/sd/aspeed_sdhci.h"
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#include "hw/usb/hcd-ehci.h"
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#include "qom/object.h"
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#define ASPEED_SPIS_NUM 2
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#define ASPEED_EHCIS_NUM 2
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@ -34,7 +35,7 @@
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#define ASPEED_CPUS_NUM 2
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#define ASPEED_MACS_NUM 4
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typedef struct AspeedSoCState {
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struct AspeedSoCState {
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/*< private >*/
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DeviceState parent;
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@ -60,12 +61,14 @@ typedef struct AspeedSoCState {
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AspeedGPIOState gpio_1_8v;
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AspeedSDHCIState sdhci;
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AspeedSDHCIState emmc;
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} AspeedSoCState;
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};
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typedef struct AspeedSoCState AspeedSoCState;
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#define TYPE_ASPEED_SOC "aspeed-soc"
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typedef struct AspeedSoCClass AspeedSoCClass;
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#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
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typedef struct AspeedSoCClass {
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struct AspeedSoCClass {
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DeviceClass parent_class;
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const char *name;
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@ -79,7 +82,7 @@ typedef struct AspeedSoCClass {
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const int *irqmap;
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const hwaddr *memmap;
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uint32_t num_cpus;
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} AspeedSoCClass;
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};
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#define ASPEED_SOC_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
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@ -29,12 +29,14 @@
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#include "hw/timer/bcm2835_systmr.h"
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#include "hw/usb/hcd-dwc2.h"
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#include "hw/misc/unimp.h"
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#include "qom/object.h"
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#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
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typedef struct BCM2835PeripheralState BCM2835PeripheralState;
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#define BCM2835_PERIPHERALS(obj) \
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OBJECT_CHECK(BCM2835PeripheralState, (obj), TYPE_BCM2835_PERIPHERALS)
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typedef struct BCM2835PeripheralState {
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struct BCM2835PeripheralState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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@ -70,6 +72,6 @@ typedef struct BCM2835PeripheralState {
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UnimplementedDeviceState smi;
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DWC2State dwc2;
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UnimplementedDeviceState sdramc;
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} BCM2835PeripheralState;
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};
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#endif /* BCM2835_PERIPHERALS_H */
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@ -15,8 +15,11 @@
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#include "hw/arm/bcm2835_peripherals.h"
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#include "hw/intc/bcm2836_control.h"
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#include "target/arm/cpu.h"
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#include "qom/object.h"
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#define TYPE_BCM283X "bcm283x"
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typedef struct BCM283XClass BCM283XClass;
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typedef struct BCM283XState BCM283XState;
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#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X)
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#define BCM283X_NCPUS 4
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@ -28,7 +31,7 @@
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#define TYPE_BCM2836 "bcm2836"
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#define TYPE_BCM2837 "bcm2837"
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typedef struct BCM283XState {
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struct BCM283XState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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@ -40,14 +43,14 @@ typedef struct BCM283XState {
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} cpu[BCM283X_NCPUS];
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BCM2836ControlState control;
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BCM2835PeripheralState peripherals;
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} BCM283XState;
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};
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typedef struct BCM283XInfo BCM283XInfo;
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typedef struct BCM283XClass {
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struct BCM283XClass {
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DeviceClass parent_class;
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const BCM283XInfo *info;
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} BCM283XClass;
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};
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#define BCM283X_CLASS(klass) \
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OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X)
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@ -21,14 +21,16 @@
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#include "cpu.h"
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#include "hw/timer/digic-timer.h"
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#include "hw/char/digic-uart.h"
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#include "qom/object.h"
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#define TYPE_DIGIC "digic"
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typedef struct DigicState DigicState;
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#define DIGIC(obj) OBJECT_CHECK(DigicState, (obj), TYPE_DIGIC)
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#define DIGIC4_NB_TIMERS 3
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typedef struct DigicState {
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struct DigicState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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@ -37,6 +39,6 @@ typedef struct DigicState {
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DigicTimerState timer[DIGIC4_NB_TIMERS];
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DigicUartState uart;
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} DigicState;
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};
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#endif /* HW_ARM_DIGIC_H */
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@ -27,6 +27,7 @@
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#include "hw/or-irq.h"
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#include "hw/sysbus.h"
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#include "target/arm/cpu-qom.h"
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#include "qom/object.h"
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#define EXYNOS4210_NCPUS 2
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@ -85,7 +86,7 @@ typedef struct Exynos4210Irq {
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qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
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} Exynos4210Irq;
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typedef struct Exynos4210State {
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struct Exynos4210State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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@ -101,7 +102,8 @@ typedef struct Exynos4210State {
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MemoryRegion bootreg_mem;
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I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
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qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
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} Exynos4210State;
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};
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typedef struct Exynos4210State Exynos4210State;
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#define TYPE_EXYNOS4210_SOC "exynos4210"
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#define EXYNOS4210_SOC(obj) \
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@ -32,8 +32,10 @@
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#include "hw/watchdog/wdt_imx2.h"
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#include "exec/memory.h"
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#include "target/arm/cpu.h"
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#include "qom/object.h"
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#define TYPE_FSL_IMX25 "fsl,imx25"
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typedef struct FslIMX25State FslIMX25State;
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#define FSL_IMX25(obj) OBJECT_CHECK(FslIMX25State, (obj), TYPE_FSL_IMX25)
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#define FSL_IMX25_NUM_UARTS 5
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@ -44,7 +46,7 @@
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#define FSL_IMX25_NUM_ESDHCS 2
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#define FSL_IMX25_NUM_USBS 2
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typedef struct FslIMX25State {
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struct FslIMX25State {
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/*< private >*/
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DeviceState parent_obj;
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@ -66,7 +68,7 @@ typedef struct FslIMX25State {
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MemoryRegion iram;
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MemoryRegion iram_alias;
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uint32_t phy_num;
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} FslIMX25State;
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};
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/**
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* i.MX25 memory map
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@ -28,8 +28,10 @@
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#include "hw/watchdog/wdt_imx2.h"
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#include "exec/memory.h"
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#include "target/arm/cpu.h"
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#include "qom/object.h"
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#define TYPE_FSL_IMX31 "fsl,imx31"
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typedef struct FslIMX31State FslIMX31State;
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#define FSL_IMX31(obj) OBJECT_CHECK(FslIMX31State, (obj), TYPE_FSL_IMX31)
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#define FSL_IMX31_NUM_UARTS 2
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@ -37,7 +39,7 @@
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#define FSL_IMX31_NUM_I2CS 3
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#define FSL_IMX31_NUM_GPIOS 3
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typedef struct FslIMX31State {
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struct FslIMX31State {
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/*< private >*/
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DeviceState parent_obj;
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@ -55,7 +57,7 @@ typedef struct FslIMX31State {
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MemoryRegion rom;
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MemoryRegion iram;
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MemoryRegion iram_alias;
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} FslIMX31State;
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};
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#define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
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#define FSL_IMX31_SECURE_ROM_SIZE 0x4000
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@ -34,8 +34,10 @@
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#include "hw/usb/imx-usb-phy.h"
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#include "exec/memory.h"
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#include "cpu.h"
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#include "qom/object.h"
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#define TYPE_FSL_IMX6 "fsl,imx6"
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typedef struct FslIMX6State FslIMX6State;
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#define FSL_IMX6(obj) OBJECT_CHECK(FslIMX6State, (obj), TYPE_FSL_IMX6)
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#define FSL_IMX6_NUM_CPUS 4
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@ -49,7 +51,7 @@
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#define FSL_IMX6_NUM_USB_PHYS 2
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#define FSL_IMX6_NUM_USBS 4
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typedef struct FslIMX6State {
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struct FslIMX6State {
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/*< private >*/
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DeviceState parent_obj;
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@ -74,7 +76,7 @@ typedef struct FslIMX6State {
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MemoryRegion ocram;
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MemoryRegion ocram_alias;
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uint32_t phy_num;
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} FslIMX6State;
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};
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#define FSL_IMX6_MMDC_ADDR 0x10000000
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@ -38,8 +38,10 @@
|
|||
#include "hw/usb/imx-usb-phy.h"
|
||||
#include "exec/memory.h"
|
||||
#include "cpu.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_FSL_IMX6UL "fsl,imx6ul"
|
||||
typedef struct FslIMX6ULState FslIMX6ULState;
|
||||
#define FSL_IMX6UL(obj) OBJECT_CHECK(FslIMX6ULState, (obj), TYPE_FSL_IMX6UL)
|
||||
|
||||
enum FslIMX6ULConfiguration {
|
||||
|
|
@ -60,7 +62,7 @@ enum FslIMX6ULConfiguration {
|
|||
FSL_IMX6UL_NUM_USBS = 2,
|
||||
};
|
||||
|
||||
typedef struct FslIMX6ULState {
|
||||
struct FslIMX6ULState {
|
||||
/*< private >*/
|
||||
DeviceState parent_obj;
|
||||
|
||||
|
|
@ -89,7 +91,7 @@ typedef struct FslIMX6ULState {
|
|||
MemoryRegion ocram_alias;
|
||||
|
||||
uint32_t phy_num[FSL_IMX6UL_NUM_ETHS];
|
||||
} FslIMX6ULState;
|
||||
};
|
||||
|
||||
enum FslIMX6ULMemoryMap {
|
||||
FSL_IMX6UL_MMDC_ADDR = 0x80000000,
|
||||
|
|
|
|||
|
|
@ -39,8 +39,10 @@
|
|||
#include "hw/pci-host/designware.h"
|
||||
#include "hw/usb/chipidea.h"
|
||||
#include "cpu.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_FSL_IMX7 "fsl,imx7"
|
||||
typedef struct FslIMX7State FslIMX7State;
|
||||
#define FSL_IMX7(obj) OBJECT_CHECK(FslIMX7State, (obj), TYPE_FSL_IMX7)
|
||||
|
||||
enum FslIMX7Configuration {
|
||||
|
|
@ -59,7 +61,7 @@ enum FslIMX7Configuration {
|
|||
FSL_IMX7_NUM_ADCS = 2,
|
||||
};
|
||||
|
||||
typedef struct FslIMX7State {
|
||||
struct FslIMX7State {
|
||||
/*< private >*/
|
||||
DeviceState parent_obj;
|
||||
|
||||
|
|
@ -82,7 +84,7 @@ typedef struct FslIMX7State {
|
|||
ChipideaState usb[FSL_IMX7_NUM_USBS];
|
||||
DesignwarePCIEHost pcie;
|
||||
uint32_t phy_num[FSL_IMX7_NUM_ETHS];
|
||||
} FslIMX7State;
|
||||
};
|
||||
|
||||
enum FslIMX7MemoryMap {
|
||||
FSL_IMX7_MMDC_ADDR = 0x80000000,
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_ARM_LINUX_BOOT_IF "arm-linux-boot-if"
|
||||
typedef struct ARMLinuxBootIfClass ARMLinuxBootIfClass;
|
||||
#define ARM_LINUX_BOOT_IF_CLASS(klass) \
|
||||
OBJECT_CLASS_CHECK(ARMLinuxBootIfClass, (klass), TYPE_ARM_LINUX_BOOT_IF)
|
||||
#define ARM_LINUX_BOOT_IF_GET_CLASS(obj) \
|
||||
|
|
@ -18,7 +19,7 @@
|
|||
|
||||
typedef struct ARMLinuxBootIf ARMLinuxBootIf;
|
||||
|
||||
typedef struct ARMLinuxBootIfClass {
|
||||
struct ARMLinuxBootIfClass {
|
||||
/*< private >*/
|
||||
InterfaceClass parent_class;
|
||||
|
||||
|
|
@ -35,6 +36,6 @@ typedef struct ARMLinuxBootIfClass {
|
|||
* (or for a CPU which doesn't support TrustZone)
|
||||
*/
|
||||
void (*arm_linux_init)(ARMLinuxBootIf *obj, bool secure_boot);
|
||||
} ARMLinuxBootIfClass;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,8 +30,10 @@
|
|||
#include "hw/misc/msf2-sysreg.h"
|
||||
#include "hw/ssi/mss-spi.h"
|
||||
#include "hw/net/msf2-emac.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_MSF2_SOC "msf2-soc"
|
||||
typedef struct MSF2State MSF2State;
|
||||
#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
|
||||
|
||||
#define MSF2_NUM_SPIS 2
|
||||
|
|
@ -44,7 +46,7 @@
|
|||
*/
|
||||
#define MSF2_NUM_TIMERS 2
|
||||
|
||||
typedef struct MSF2State {
|
||||
struct MSF2State {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
/*< public >*/
|
||||
|
|
@ -64,6 +66,6 @@ typedef struct MSF2State {
|
|||
MSSTimerState timer;
|
||||
MSSSpiState spi[MSF2_NUM_SPIS];
|
||||
MSF2EmacState emac;
|
||||
} MSF2State;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -17,14 +17,16 @@
|
|||
#include "hw/gpio/nrf51_gpio.h"
|
||||
#include "hw/nvram/nrf51_nvm.h"
|
||||
#include "hw/timer/nrf51_timer.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_NRF51_SOC "nrf51-soc"
|
||||
typedef struct NRF51State NRF51State;
|
||||
#define NRF51_SOC(obj) \
|
||||
OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC)
|
||||
|
||||
#define NRF51_NUM_TIMERS 3
|
||||
|
||||
typedef struct NRF51State {
|
||||
struct NRF51State {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
|
|
@ -50,6 +52,6 @@ typedef struct NRF51State {
|
|||
|
||||
MemoryRegion container;
|
||||
|
||||
} NRF51State;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include "hw/input/tsc2xxx.h"
|
||||
#include "target/arm/cpu-qom.h"
|
||||
#include "qemu/log.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
# define OMAP_EMIFS_BASE 0x00000000
|
||||
# define OMAP2_Q0_BASE 0x00000000
|
||||
|
|
@ -69,10 +70,10 @@ void omap_clk_reparent(omap_clk clk, omap_clk parent);
|
|||
|
||||
/* omap_intc.c */
|
||||
#define TYPE_OMAP_INTC "common-omap-intc"
|
||||
typedef struct omap_intr_handler_s omap_intr_handler;
|
||||
#define OMAP_INTC(obj) \
|
||||
OBJECT_CHECK(omap_intr_handler, (obj), TYPE_OMAP_INTC)
|
||||
|
||||
typedef struct omap_intr_handler_s omap_intr_handler;
|
||||
|
||||
/*
|
||||
* TODO: Ideally we should have a clock framework that
|
||||
|
|
@ -93,9 +94,9 @@ void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk);
|
|||
|
||||
/* omap_i2c.c */
|
||||
#define TYPE_OMAP_I2C "omap_i2c"
|
||||
typedef struct OMAPI2CState OMAPI2CState;
|
||||
#define OMAP_I2C(obj) OBJECT_CHECK(OMAPI2CState, (obj), TYPE_OMAP_I2C)
|
||||
|
||||
typedef struct OMAPI2CState OMAPI2CState;
|
||||
|
||||
/* TODO: clock framework (see above) */
|
||||
void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk);
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include "exec/memory.h"
|
||||
#include "target/arm/cpu-qom.h"
|
||||
#include "hw/pcmcia.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
/* Interrupt numbers */
|
||||
# define PXA2XX_PIC_SSP3 0
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/pci/pci.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define SMMU_PCI_BUS_MAX 256
|
||||
#define SMMU_PCI_DEVFN_MAX 256
|
||||
|
|
@ -102,7 +103,7 @@ typedef struct SMMUIOTLBKey {
|
|||
uint8_t level;
|
||||
} SMMUIOTLBKey;
|
||||
|
||||
typedef struct SMMUState {
|
||||
struct SMMUState {
|
||||
/* <private> */
|
||||
SysBusDevice dev;
|
||||
const char *mrtypename;
|
||||
|
|
@ -116,9 +117,10 @@ typedef struct SMMUState {
|
|||
QLIST_HEAD(, SMMUDevice) devices_with_notifiers;
|
||||
uint8_t bus_num;
|
||||
PCIBus *primary_bus;
|
||||
} SMMUState;
|
||||
};
|
||||
typedef struct SMMUState SMMUState;
|
||||
|
||||
typedef struct {
|
||||
struct SMMUBaseClass {
|
||||
/* <private> */
|
||||
SysBusDeviceClass parent_class;
|
||||
|
||||
|
|
@ -126,7 +128,8 @@ typedef struct {
|
|||
|
||||
DeviceRealize parent_realize;
|
||||
|
||||
} SMMUBaseClass;
|
||||
};
|
||||
typedef struct SMMUBaseClass SMMUBaseClass;
|
||||
|
||||
#define TYPE_ARM_SMMU "arm-smmu"
|
||||
#define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU)
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
|
||||
#include "hw/arm/smmu-common.h"
|
||||
#include "hw/registerfields.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region"
|
||||
|
||||
|
|
@ -32,7 +33,7 @@ typedef struct SMMUQueue {
|
|||
uint8_t log2size;
|
||||
} SMMUQueue;
|
||||
|
||||
typedef struct SMMUv3State {
|
||||
struct SMMUv3State {
|
||||
SMMUState smmu_state;
|
||||
|
||||
uint32_t features;
|
||||
|
|
@ -61,7 +62,8 @@ typedef struct SMMUv3State {
|
|||
|
||||
qemu_irq irq[4];
|
||||
QemuMutex mutex;
|
||||
} SMMUv3State;
|
||||
};
|
||||
typedef struct SMMUv3State SMMUv3State;
|
||||
|
||||
typedef enum {
|
||||
SMMU_IRQ_EVTQ,
|
||||
|
|
@ -70,14 +72,15 @@ typedef enum {
|
|||
SMMU_IRQ_GERROR,
|
||||
} SMMUIrq;
|
||||
|
||||
typedef struct {
|
||||
struct SMMUv3Class {
|
||||
/*< private >*/
|
||||
SMMUBaseClass smmu_base_class;
|
||||
/*< public >*/
|
||||
|
||||
DeviceRealize parent_realize;
|
||||
DeviceReset parent_reset;
|
||||
} SMMUv3Class;
|
||||
};
|
||||
typedef struct SMMUv3Class SMMUv3Class;
|
||||
|
||||
#define TYPE_ARM_SMMUV3 "arm-smmuv3"
|
||||
#define ARM_SMMUV3(obj) OBJECT_CHECK(SMMUv3State, (obj), TYPE_ARM_SMMUV3)
|
||||
|
|
|
|||
|
|
@ -32,8 +32,10 @@
|
|||
#include "hw/or-irq.h"
|
||||
#include "hw/ssi/stm32f2xx_spi.h"
|
||||
#include "hw/arm/armv7m.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_STM32F205_SOC "stm32f205-soc"
|
||||
typedef struct STM32F205State STM32F205State;
|
||||
#define STM32F205_SOC(obj) \
|
||||
OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC)
|
||||
|
||||
|
|
@ -47,7 +49,7 @@
|
|||
#define SRAM_BASE_ADDRESS 0x20000000
|
||||
#define SRAM_SIZE (128 * 1024)
|
||||
|
||||
typedef struct STM32F205State {
|
||||
struct STM32F205State {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
/*< public >*/
|
||||
|
|
@ -63,6 +65,6 @@ typedef struct STM32F205State {
|
|||
STM32F2XXSPIState spi[STM_NUM_SPIS];
|
||||
|
||||
qemu_or_irq *adc_irqs;
|
||||
} STM32F205State;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -33,8 +33,10 @@
|
|||
#include "hw/or-irq.h"
|
||||
#include "hw/ssi/stm32f2xx_spi.h"
|
||||
#include "hw/arm/armv7m.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_STM32F405_SOC "stm32f405-soc"
|
||||
typedef struct STM32F405State STM32F405State;
|
||||
#define STM32F405_SOC(obj) \
|
||||
OBJECT_CHECK(STM32F405State, (obj), TYPE_STM32F405_SOC)
|
||||
|
||||
|
|
@ -48,7 +50,7 @@
|
|||
#define SRAM_BASE_ADDRESS 0x20000000
|
||||
#define SRAM_SIZE (192 * 1024)
|
||||
|
||||
typedef struct STM32F405State {
|
||||
struct STM32F405State {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
/*< public >*/
|
||||
|
|
@ -68,6 +70,6 @@ typedef struct STM32F405State {
|
|||
MemoryRegion sram;
|
||||
MemoryRegion flash;
|
||||
MemoryRegion flash_alias;
|
||||
} STM32F405State;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -37,6 +37,7 @@
|
|||
#include "hw/block/flash.h"
|
||||
#include "sysemu/kvm.h"
|
||||
#include "hw/intc/arm_gicv3_common.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define NUM_GICV2M_SPIS 64
|
||||
#define NUM_VIRTIO_TRANSPORTS 32
|
||||
|
|
@ -115,7 +116,7 @@ typedef struct MemMapEntry {
|
|||
hwaddr size;
|
||||
} MemMapEntry;
|
||||
|
||||
typedef struct {
|
||||
struct VirtMachineClass {
|
||||
MachineClass parent;
|
||||
bool disallow_affinity_adjustment;
|
||||
bool no_its;
|
||||
|
|
@ -126,9 +127,10 @@ typedef struct {
|
|||
bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
|
||||
bool kvm_no_adjvtime;
|
||||
bool acpi_expose_flash;
|
||||
} VirtMachineClass;
|
||||
};
|
||||
typedef struct VirtMachineClass VirtMachineClass;
|
||||
|
||||
typedef struct {
|
||||
struct VirtMachineState {
|
||||
MachineState parent;
|
||||
Notifier machine_done;
|
||||
DeviceState *platform_bus_dev;
|
||||
|
|
@ -162,7 +164,8 @@ typedef struct {
|
|||
DeviceState *gic;
|
||||
DeviceState *acpi_dev;
|
||||
Notifier powerdown_notifier;
|
||||
} VirtMachineState;
|
||||
};
|
||||
typedef struct VirtMachineState VirtMachineState;
|
||||
|
||||
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
|
||||
|
||||
|
|
|
|||
|
|
@ -20,8 +20,10 @@
|
|||
#include "hw/dma/xlnx-zdma.h"
|
||||
#include "hw/net/cadence_gem.h"
|
||||
#include "hw/rtc/xlnx-zynqmp-rtc.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_XLNX_VERSAL "xlnx-versal"
|
||||
typedef struct Versal Versal;
|
||||
#define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL)
|
||||
|
||||
#define XLNX_VERSAL_NR_ACPUS 2
|
||||
|
|
@ -31,7 +33,7 @@
|
|||
#define XLNX_VERSAL_NR_SDS 2
|
||||
#define XLNX_VERSAL_NR_IRQS 192
|
||||
|
||||
typedef struct Versal {
|
||||
struct Versal {
|
||||
/*< private >*/
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
|
|
@ -74,7 +76,7 @@ typedef struct Versal {
|
|||
MemoryRegion *mr_ddr;
|
||||
uint32_t psci_conduit;
|
||||
} cfg;
|
||||
} Versal;
|
||||
};
|
||||
|
||||
/* Memory-map and IRQ definitions. Copied a subset from
|
||||
* auto-generated files. */
|
||||
|
|
|
|||
|
|
@ -32,8 +32,10 @@
|
|||
#include "hw/rtc/xlnx-zynqmp-rtc.h"
|
||||
#include "hw/cpu/cluster.h"
|
||||
#include "target/arm/cpu.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
|
||||
typedef struct XlnxZynqMPState XlnxZynqMPState;
|
||||
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
|
||||
TYPE_XLNX_ZYNQMP)
|
||||
|
||||
|
|
@ -73,7 +75,7 @@
|
|||
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
|
||||
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
|
||||
|
||||
typedef struct XlnxZynqMPState {
|
||||
struct XlnxZynqMPState {
|
||||
/*< private >*/
|
||||
DeviceState parent_obj;
|
||||
|
||||
|
|
@ -112,6 +114,6 @@ typedef struct XlnxZynqMPState {
|
|||
bool virt;
|
||||
/* Has the RPU subsystem? */
|
||||
bool has_rpu;
|
||||
} XlnxZynqMPState;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue